Compaq Computer Corporation, Inc.

Advanced Micro Devices Corporation

Hewlett-packard Development Company, L.P.

Hewlett Packard Enterprise Development LP

Gary W Thome

Michael J Collins

John Edward Larson

John S Thayer

Michael P Moriarty

Paul A Santeler

Jens K Ramsey

Brian E Longhenry

John Gregory Favor

Frederick Daniel Weber

John A Landry

Basem Abu Ayash

Randy M Bonella

Mustafa A Hamid

Sompong Paul Olarig

Kevin B Leigh

Paul R Culley

Theodore F Emerson

David F Heinrich

Alan L Goodrum

Vincent Hung Nguyen

Andrew Brown

David R Wooten

Jeffrey C Stevens

Roger E Tipley

Ronald Timothy Horan

Michael S Bunker

James H Nuckols

Aland B Adams

Brian B Tucker

Gary L Brasher

Lee B Hinkle

Earl C Reeves

Christine G Cash

John Sarni

Harry R Roger, Jr

Kameron H Ayati

David M Olson

In one example, a system for embedded image management includes a blade enclosure that includes a set of server blades, an embedded image management appliance coupled to the blade enclosure, comprising: an image repository stored in a memory resource, an appliance operating system that operates on the memory resource, and an image resource manager that operates on the appliance operating system.

Embedded image management

Systems and methods for flow control within a Serial Peripheral Interface without additional signal lines are included herein. In one example, a method includes generating a flow control command. The method also includes sending the flow control command from a master device to a slave device with a Serial Peripheral Interface. In addition, the method includes sending a memory address from the master device to the slave device. Furthermore, the method includes detecting a ready indicator in the master device. The method also includes waiting to receive a ready indicator and communicating with the slave device in response to the ready indicator.

Flow control for a Serial Peripheral Interface bus

A routable operand and selectable operation processor multimedia extension unit is employed to draw lines in a video system using an efficient, parallel technique. A first series of integral y pixel values and error values are calculated according to Bresenham's line drawing algorithm. Then, subsequent pixels and error values are calculated in parallel based on the previously calculated values.

Line drawing using operand routing and operation selective multimedia extension unit

A multimedia extension unit (MEU) is provided for performing various multimedia-type operations. The MEU can be coupled either through a coprocessor bus or a local CPU bus to a conventional processor. The MEU employs vector registers, a vector ALU, and an operand routing unit (ORU) to perform a maximum number of the multimedia operations within as few instruction cycles as possible. Complex algorithms are readily performed by arranging operands upon the vector ALU in accordance with the desired algorithm flowgraph. The ORU aligns the operands within partitioned slots or sub-slots of the vector registers using vector instructions unique to the MEU. At the output of the ORU, operand pairs from vector source or destination registers can be easily routed and combined at the vector ALU. The MEU may include a plurality of ALUs, registers partitioned into slots, and a decode unit for decoding an instruction specifying operands from any slot from one register and from a fixed slot of another register as well as different operations to be performed by the ALUs on the operands.

Decoding operands for multimedia applications instruction coded with

An apparatus for monitoring and decoding processor bus cycles and flushing a second level cache upon decoding a special flush acknowledge cycle. The CPU preferably includes an internal cache and a flush input for receiving a signal commanding the CPU to flush its internal cache. After flushing its cache by performing any necessary cycles to write back dirty data to main memory, the CPU performs a special flush acknowledge cycle to inform external devices that the flush procedure has been completed. A cache controller detects the flush acknowledge cycle and provides a flush signal to the second level cache. The cache controller then provides an end of cycle signal to the CPU to indicate that the flush cycle has been acknowledged.

Hierarchical cache system flushing scheme based on monitoring and

A multimedia extension unit (MEU) is provided for performing various multimedia-type operations. The MEU may be coupled either through a coprocessor bus or a local CPU bus to a conventional processor. The MEU employs vector registers, a vector ALU, and an operand routing unit (ORU) to perform a maximum number of the multimedia operations within as few instruction cycles as possible. Complex algorithms are readily performed by arranging operands upon the vector ALU in accordance with the desired algorithm flowgraph. The ORU aligns the operands within partitioned slots or sub-slots of the vector registers using vector instructions unique to the MEU. At the output of the ORU, operand pairs from vector source or destination registers may be easily routed and combined at the vector ALU. The vector instructions employ special load/store instructions in combination with numerous operational instructions to carry out concurrent multimedia operations on the aligned operands. In one embodiment, an arithmetic logic unit may be partitioned into at least two logic portions. A first logic portion may be coupled to receive a first operand from a fixed slot of a first register and a second operand from any slot of a second register. A second logic portion may be coupled to receive a third operand from a fixed slot of the first register and a fourth operand from any slot of the second register. The first logic portion may perform an arithmetic operation dissimilar from the second logic portion.

Computer having multimedia operations executable as two distinct sets of

A multimedia extension unit (MEU) is provided for performing various multimedia-type operations. The MEU can be coupled either through a coprocessor bus or a local CPU bus to a conventional processor. The MEU employs vector registers, a vector ALU, and an operand routing unit (ORU) to perform a maximum number of the multimedia operations within as few instruction cycles as possible. Complex algorithms are readily performed by arranging operands upon the vector ALU in accordance with the desired algorithm flowgraph. The ORU aligns the operands within partitioned slots or sub-slots of the vector registers using vector instructions unique to the MEU. At the output of the ORU, operand pairs from vector source or destination registers can be easily routed and combined at the vector ALU. The vector instructions employ special load/store instructions in combination with numerous operational instructions to carry out concurrent multimedia operations on the aligned operands. In one embodiment, multiple ALUs may each receive one operand from a fixed source register slot location, where the fixed slot location may be different for each ALU. The operand routing may provide another operand from any source register slot location for another input to each respective ALU.

System and method for routing one operand to arithmetic logic units from

A routable operand and selectable operation processor multimedia extension unit is employed to motion compensate MPEG video using improved vector processing. A vector processing unit executes an add and divide instruction that adds two vector registers and divides the result in a single instruction. This is implemented through loading a first vector register with a first plurality of elements from a source block. A second vector register is then loaded with a second plurality of elements that are adjacent to the first plurality of elements. The add and divide instruction is then executed on the first and second vector registers, yielding an interpolated source element that is stored in a resultant vector register.

MPEG motion compensation using operand routing and performing add and

A memory controller which provides a series of queues between the processor and the PCI bus and the memory system. Memory coherency is maintained in two different ways. Before any read operations are accepted from the PCI bus, both of the posting queues must be empty. A content addressable memory (CAM) is utilized as the PCI to memory queue. When the processor performs a read request, the CAM is checked to determine if one of the pending write operations in the PCI to memory queue is to the same address as the read operation of the processor. If so, the read operation is not executed until the PCI memory queue is cleared of the write. To resolve the problem of aborting a Memory Read Multiple operation, an abort signal from the PCI bus interface is received and as soon thereafter as can be done the read ahead cycle is terminated, even though the read ahead cycle has not fully completed. The memory controller has improved prediction rules based on whether the cycle is coming from the processor or is coming from the PCI bus to allow more efficient precharging when PCI bus cycles are used. The memory controller is highly programmable for multiple speeds and types of processors and several speeds of memory devices. The memory controller includes a plurality of registers that specify number of clock periods for the particular portions of a conventional DRAM cycle which are used to control state machine operations.

Memory controller having precharge prediction based on processor and PCI

A memory controller which provides a series of queues between the processor and the PCI bus and the memory system. Memory coherency is maintained in two different ways. Before any read operations are accepted from the PCI bus, both of the posting queues must be empty. A content addressable memory (CAM) is utilized as the PCI to memory queue. When the processor performs a read request, the CAM is checked to determine if one of the pending write operations in the PCI to memory queue is to the same address as the read operation of the processor. If so, the read operation is not executed until the PCI memory queue is cleared of the write. To resolve the problem of aborting a Memory Read Multiple operation, an abort signal from the PCI bus interface is received and as soon thereafter as can be done the read ahead cycle is terminated, even though the read ahead cycle has not fully completed. The memory controller has improved prediction rules based on whether the cycle is coming from the processor or is coming from the PCI bus to allow more efficient precharging when PCI bus cycles are used. The memory controller is highly programmable for multiple speeds and types of processors and several speeds of memory devices.

Memory controller including write posting queues, bus read control

A signal represented as a matrix of input values is adaptively filtered using a processor with a multimedia extension unit. A plurality of coefficients are loaded into a first vector register and input values are loaded into a second vector register. Next, for each of the coefficients in the first vector register, (1) a single cycle vector multiply-accumulate operation is performed between the selected coefficient and the input values stored in the second vector register and the result is stored in a third register; (2) a partition-shift on input values in the second vector register is then performed and a new input value is then moved into the second vector register. After each of the four loaded coefficients have been processed, the results are saved and the operation is repeated until all input values in the matrix have been processed.

Enhanced adaptive filtering technique

A method and apparatus for designing a computer system which supports multiple processors of different types. A processor base board is separately connectable to a system board. The processor base board includes a number of connectors for receiving processor boards. The processor boards include a processor and, if necessary, a voltage regulator and voltage level converters. A right angle single edge contact connector is used on a Pentium II board to significantly reduce spacing requirements of adjacent processor boards. A conventional pin grid array type socket is used for a Pentium Pro processor board. A special mapping of bus request signals is disclosed for supporting four Pentium Pro processors or two Pentium II processors without requiring changes to the processor base board.

System design to support either Pentium Pro processors, Pentium II

A core logic chip set is provided in a computer system to provide a bridge between host and memory buses and an accelerated graphics port ('AGP') bus adapted for operation of two AGP devices, or one AGP device and one peripheral component interconnect ('PCI') device. A common AGP bus having provisions for the PCI and AGP interface signals is connected to the core logic chip set and the AGP and/or PCI device(s). The core logic chip set has an AGP/PCI arbiter having Request ('REQ') and Grant ('GNT') signal lines for each AGP and/or PCI device connected to the AGP bus. Another embodiment has a plurality of AGP buses for a plurality of AGP devices. This allows concurrent operation for AGP devices connected to different AGP buses. Two of the AGP buses may be combined to connect to one 64 bit PCI device.

Computer bridge interfaces for accelerated graphics port and peripheral

A multimedia extension unit (MEU) is provided for performing various multimedia-type operations. The MEU can be coupled either through a coprocessor bus or a local CPU bus to a conventional processor. The MEU employs vector registers, a vector ALU, and an operand routing unit (ORU) to perform a maximum number of the multimedia operations within as few instruction cycles as possible. Complex algorithms are readily performed by arranging operands upon the vector ALU in accordance with the desired algorithm flowgraph. The ORU aligns the operands within partitioned slots or sub-slots of the vector registers using vector instructions unique to the MEU. At the output of the ORU, operand pairs from vector source or destination registers can be easily routed and combined at the vector ALU. The vector instructions employ special load/store instructions in combination with numerous operational instructions to carry out concurrent multimedia operations on the aligned operands.

System and method for routing operands within partitions of a source

An apparatus and a method for massaging audio signal perform interpolation, dynamic filtering, and panning on the audio signal represented as a matrix of input values. In the interpolation process, the input values are loaded into first and second vector registers, while fractional coefficients are loaded into a third vector register. Next, the first vector register is subtracted from the second vector register. Additionally, in a single operation, the routine performs a vector multiply operation between the second and third registers and accumulates the result of the vector multiply operation in the second register. The results are saved and the process is repeated until all input values in the matrix have been processed. In the dynamic filtering process, after the data loading step, for each slot in said vector register, the routine performs a multiply operation between the filter coefficient and the slot of the vector register and accumulates the result of the multiply operation in the slot of the second register in a single clock cycle while it retains data of the remaining slots in the vector register in the same clock cycle. The results are saved and the process is repeated until all input values in the matrix have been processed. In the stretching process, after loading data in the appropriate vector register, the routine copies the content of each slot of the vector register into consecutive pair of slots on a second vector register and when the second vector register is full, copies the content of each of the remaining slots in the first vector register into consecutive pairs of slots on a third register. In the panning process, the routine performs a vector multiply operation between the first vector register and a coefficient vector register for each slot in the first vector register. This vector multiply operation is preferably a 32-bit vector multiply operation which is broken down into a low order extended precision multiply accumulate operation and a high order extended precision multiply accumulate operation.

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Tomball, TX, United States of America

Gary W Thome