Cypress Semiconductor Corporation

Silicon Light Machines Corporation

Gary W Green

Gregory David Miller

Mathew R Arcoleo

Shailesh Shah

Mike Bruner

Lawrence Ragan

John Q Torode

Piyush Sevalia

T J Rodgers

Raymong Leong

An apparatus that may be configured to generate a wireless radio signal in response to one or more first data signals. The wireless radio signal may comprise a single frequency hopping sequence configured to support one or more peripheral wireless network devices. The apparatus may also be configured to generate the one or more first data signals in response to the wireless radio signal.

Integrated radio frequency interface

One embodiment disclosed relates to a method for sealing an active area of a surface acoustic wave (SAW) device on a wafer. The method includes providing a sacrificial material over at least the active area of the SAW device, depositing a seal coating over the wafer so that the seal coating covers the sacrificial material, and replacing the sacrificial material with a target atmosphere. Another embodiment disclosed relates to an SAW device sealed at the wafer level (i.e. prior to separation of the die from the wafer). The device includes an active area to be protected, an electrical contact area, and a lithographically-formed structure sealing at least the active area and leaving at least a portion of the electrical contact area exposed.

Method for sealing an active area of a surface acoustic wave device on a wafer

A CAM including a set of priority registers for storing information from one port and a set of non-priority registers for storing information from a second port. The CAM also includes a memory array that is coupled to both sets of registers. A port arbiter within the CAM determines which set of registers is given access to the memory array. Also described is a method for controlling access to the memory array. A lock interval is indicated before the priority registers initiate access to the memory array. During the lock interval, access to the memory by the non-priority registers is delayed if the access cannot be completed before the priority registers begin access.

Dual-port content addressable memory

A method and circuit for hiding a refresh of DRAM cells in a memory device. One embodiment of the circuit includes a selection circuit configured to select a first row of DRAM cells in the memory circuit in response to an active control signal. As a result, data may be read from or written to at least one of the DRAM cells in the first row. The selection circuit is also configured to couple a refresh address to a second row of DRAM cells in the memory circuit in response to an inactive state control signal. The second row of cells is refreshed when the selection circuit accesses the second row. For one embodiment, the DRAM cells are four transistor DRAM cells.

Dram with hidden refresh

A method of limiting or translating the voltages of input signals, and of generating output signals such that the input's high state and low state differ by a different voltage than the output's high and low state. The present invention also teaches a system comprising a level translator circuit having level translators controlled by an operational amplifier or by a Zener diode that regulates the voltage level on one side of the translators, the other side of the translators being regulated by an external power supply. The operational amplifier or Zener diode, in some embodiments of the present invention, ensures that the second side of the level translators are limited to a given reference voltage. Often, a resistor is connected to the Zener diode or to the output of the operational amplifier, and in some embodiments a resistor-capacitor network removes higher-frequency components from the voltage supply. The invention includes a system level embodiment, in which the voltage level translators protect a memory and bus from voltage levels that would otherwise cause damage.

Growing community of inventors

Pleasanton, CA, United States of America

Gary W Green