Intel Corporation

Gary W Brady

David G Ellis

Ashok N Kabadi

Michael T White

Harry L Hampton, Iii

William O Brooks

Roger R Rees

Christopher P Swider

Andy Groves

Pete Nevard

Jerry Moberly

Apparatus and methods for connecting a device to an integrated circuit. The apparatus includes an insulating substrate that has two major sides and a number of sites for housing components. Each site has a first node on one of the two sides of the insulating substrate and a second node on the other of the two sides of the insulating substrate. Each site also has components that are aligned normal to the sides of the insulating substrate and are connected to the nodes at the site. Such apparatus are useful as adapters for testing an integrated circuit, such as connecting a test device to the integrated circuit with the adapter and observing and/or driving signals through the adapter.

Component array adapter

An automatic clock calibration circuit includes a source of clock signals and an equal number of corresponding clock reference signals. Corresponding delay elements are connected between the source and the load driven by each of the clock signals. A phase frequency detector detects the phase differences between each clock signal, at the point at which it is applied to its load, and its corresponding clock reference signal. A microcontroller adjusts the delay of the delay elements according to the detected phase differences.

Automatic clock calibration circuit

A number of detection circuits, one for each source of control signal set inputs, and a high speed resolution circuit, are provided for resolving multiple control signal inputs into a single stable, predictable, and useful output signal. The detection circuits detect active control signals in the various control signal set inputs, and generate detected signals. The high speed state resolution circuit generates an output signal, conditionally changing the output state based on the detected signals and the current state being output. When deciding whether to change the output state, the high speed resolution circuit considers only the detected signals applicable to the current output state and responds accordingly, ignoring all other detected signals that are not applicable. The detection circuits and the resolution circuit are coordinated in timings, ensuring proper resolution.

Circuitry for resolving multiple asynchronous state inputs

Data instrumentation system having circuitry for resolving multiple

A delay chain having a known number of delay elements providing various delayed outputs of its input, a first and a second register set, and preferably, an array of multiplexors, are provided to measure the frequency of a digital signal, and the high and low time of its period. The digital signal to be measured is provided to the delay chain as input. A first and a second sample of the various delayed outputs are taken at the beginning and the end of a known time period, and stored in the first and second registers, one delayed output per register bit. The sample results stored in the register sets are read out through the multiplexors, and used to determine the frequency of the digital signal being measured, and the high and low time of its period.

Method and apparatus for measuring frequency and high/low time of a

A first and a second input generating circuits, a first and a second set of counters, and a first and a second comparison circuits are provided to test whether the frequencies of a first and a second periodic digital signal are symmetric. The first and second input generating circuits generate enable inputs for the first and second sets of counters using the first and second digital signals respectively. The first and second sets of counters count the first and second digital signals while the enable inputs are provided. The first comparison circuit monitors the first set of counters, and stops both input generating circuits from providing further enable inputs to both sets of counters, after the first set of counters reaches a predetermined level, thereby stopping both sets of counters from further counting. The second comparison circuit monitors the second set of counters, and issues a control signal indicating the first and second digital signals are symmetric to each other in frequency, if the second set of counters also stops substantially at the predetermined level, i.e. within an acceptable threshold.

Method and apparatus for testing frequency symmetry of digital signals

The invention is for improving the performance of a microprocessor system by reducing the skew between the system clock and critical control signals. Reduction in this skew reduces or eliminates the need for waitstates on data accesses to random access memory devices thereby improving system performance. A clock is programmed to function as an asynchronous state machine to generate the clock signals and the memory device chip select. A clock source from an oscillator is input to the PAL. This clock source is buffered by the and presented at the PAL outputs as the system clock. The memory device chip select is also generated inside this using the source clock and other signals generated inside the PAL.

Single PAL circuit generating system clock and control signals to

Each of the remote high speed circuits of a digital system is provided with a sync pulse generation circuit for generating periodic sync pulses with a predetermined periodicity using a control value. Additionally, each of the remote high speed circuits is further provided with a sampling circuit for sampling the sync pulse generation control value, a comparison circuit for determining whether each of the sampled sync pulse generation control values are consistent, and an adjustment circuit for adjusting the sync pulse generation control value of the particular remote high speed circuit. Furthermore, a sync pulse generation coordinator comprising a clock selection circuit, a delay line, a delayed clock selection circuit, and a coordination pulse generation circuit is provided to the digital system for generating periodic coordination pulses. The periodic coordination pulses are used to control the sampling and comparison. A different delayed reference clock is used to generate the coordination pulses to control the sampling and comparison until a delayed reference clock that leads to consistent samples of control values for all remote high speed circuits is found. Once consistent sampling results are achieved, the sync pulse generation control values of the remote high speed circuits are adjusted accordingly using the adjustment circuits. The process is repeated until all sampled results are consistent and synchronized. The sampling is then continued to monitor for loss of synchronization.

Method and apparatus for synchronizing periodic sync pulse generations

An address converter that reduces the number of address bit changes between successive sequential addresses is provided to a RAM address bus for a sequentially accessed RAM. In the presently preferred embodiment, the address converter comprises a plurality of XOR gates for converting the access addresses into gray coded access addresses having at most one address bit change between successive access addresses. As a result, the power consumed and the noise generated over the address bus is reduced, thereby conserving power available and minimizing device package pins required by the digital system having the RAM and the RAM address bus.

RAM addressing apparatus with lower power consumption and less noise

Each data sending high speed circuit generating and sending a stream of data slices and a stream of clock pulses is provided with a sync pulse generation circuit for synchronously generating and sending an accompanying stream of periodic sync pulses. The various streams of data slices, clock pulses, and periodic sync pulses incur varying amount of delays as they travel from the data sending high speed circuits to a data acquisition circuit. The data acquisition high speed circuit is provided with a plurality of circular buffer chains of appropriate length for independently buffering the skewed data slices until all corresponding data slices have been received and buffered, and then concurrently reading the buffered corresponding data slices out of the circular buffer chains. The data acquisition high speed circuit is also provided with a plurality of corresponding independent write address generators and a common read address generator for generating the independent write buffer addressed and the synchronized read buffer addresses using the data clocks and the periodic sync pulses. As a result, the skewed data slices are deskewed or resynchronized as they are read out of the circular buffer chain.

Method and apparatus for deskewing/resynchronizing data slices with

A digital clock reconstruction circuit comprising a first flip flop, a programmable delay chain, and a first assembly of gates is provided to digitally compensate an entering digital clock's skew for a high speed digital circuit by digitally reconstructing the entering clock. The reconstructed clock will also provide the minimum amount of high and low time in a period required by the components of the high speed circuit. Additionally, at least one measurement or comparison circuit is provided for measuring the frequencies of the reconstructed clock under various delay settings of the programmable delay chain to calibrate the digital clock reconstruction circuit. Under the calibration process of the present invention, the delay setting is determined iteratively, starting from an initial setting and varying the delay setting in a predetermined manner. In the preferred embodiment, a ring oscillator is also provided to guide the selection of the starting delay setting, and multiple measurement and comparison circuits are provided. The measurement and comparison circuits are used to collect various measurements to monitor the digital clock reconstruction circuit during normal operation as well as calibrating the circuit. Furthermore, the digital clock reconstruction circuit is provided with an additional flip flop and gate assembly to generate an additional reconstructed clock. The additional reconstructed clock is periodically monitored during normal operation to provide early warning to the fact that the reconstructed clock period is drifting from 50% duty cycle symmetry.

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Aloha, OR, United States of America

Gary W Brady