Dallas Semiconductor Corporation

Maxim Integrated Products, Inc.

Microchip Technology Inc.

Gary V Zanders

Robert D Lee

Kevin E Deierling

Donald R Dias

Michael L Bolan

Francis A Scherpenberg

James M Douglass

Hal Kurkowski

Robert Michael Muchsel

Stephen M Curry

Hung Thanh Nguyen

Edward Tangkwai Ma

Sung Ung Kwak

William L Payne, Ii

Nancy Kow Iida

Guenter H Lehmann

Khankap Mounarath

Daniel D Friel

Steven N Hass

Thomas L Polgreen

Richard J DelRossi

Mark Henry Weldele

James Walling

Guenther H Lehmann

Jimmie C Vernon

Nancy Kow Lida

Mark P Enochson

Various embodiments of the invention allow to dynamically transition between clock-driven and even-driven circuit elements to enable automatic multi-mode operation to enable low-power and high-throughput applications. In certain embodiments, dynamic transitioning is accomplished through a mode control unit that evaluates input data from a number of sources to determine whether to initiate a transition. Certain embodiments take advantage of dynamic transitioning to allow for energy harvesting in a data gathering phase by switching to high power communication phase as needed. The energy harvesting scheme is particularly suited for battery-operated applications that benefit from a reduction in overall power consumption.

Systems and methods to improve energy efficiency using adaptive mode switching

Various embodiments of the invention allow to effectively reduce device and system power consumption in both active and inactive modes without compromising performance, without large area overhead, and at low cost. In certain embodiments, the reduction of power consumption is accomplished by combining circuit control techniques with power gating methods to reduce power loss due to leakage current.

System and method for adaptive power management

The invention relates to systems having linear regulators and methods of operating the systems. The system includes: a linear regulator responsive to an input voltage and operative to output a regulated voltage; a first circuit responsive to the regulated voltage and configured to operate at a first voltage difference between the regulated voltage and a ground level; and a second circuit responsive to the input voltage and the regulated voltage and configured to operate at a second voltage difference between the input voltage and the regulated voltage. The second circuit is coupled to the first circuit so that an entire portion of a current flowing through the second circuit is configured to enter into the first circuit during operation, wherein the current flowing through the second circuit bypasses the linear regulator.

Energy efficient systems having linear regulators and methods of operating the same

The invention relates to a magnetic stripe reader, and more particularly, to systems, devices and methods of directly extracting binary information embedded in a magnetic stripe using simple analog and digital signal processing techniques. Once information stored in the magnetic stripe is extracted as a F-2F waveform by the magnetic stripe reader, peaks, valleys and mid-level transition points between every consecutive peak and valley are detected. A peak-to-peak period and an average time are directly derived to determine whether the corresponding peak-to-peak transition is associated with a binary bit of '1' or '0'. This magnetic stripe reader spares a need for a multi-bit analog-to-digital converter (ADC) and a large memory, and thus, constitutes a simple and self-contained solution that may read out the binary information stored on the magnetic stripe with reduced power consumption and improved cost efficiency.

Magnetic stripe reader

An electrical circuit contains volatile states that are lost without continued application of power to circuit elements to preserve their volatile states. A first power source in the circuit provides power to the volatile state circuit for holding and preserving their volatile states. A power selection circuit is coupled to the circuit elements and has a plurality of selectable modes. A first mode of operation of the power selection circuit is selected when the circuit elements are to be operated at a first power level via the first power source which constitutes a first mode of operation. A second mode of operation is selected when the volatile state circuit elements are to be operated under a condition where the first power source is inactivated, such as, for example, during a circuit backup or standby operation. During the second mode of operation, the circuit elements volatile states are preserved via a power selection circuit that provides power from a second power source at a second power level, different from the first power level, to the volatile state circuit elements in place of the first power source.

Backup for circuits having volatile states

A backup volatile state retention circuit is provided with low leakage current for employment with a volatile memory circuit to store the value of the latter during power down of the volatile circuit or during power-down or inactivation of neighboring or peripheral circuits or due to the loss of power of any of these circuits. An example of such a volatile circuit is a memory circuit having volatile memory cells such as employed in dynamic memory core, in particular, a random access memory (RAM) in CMOS circuitry.

Backup for volatile state retention in the absence of primary circuit power

A data communication interface for transferring at least one data bit to a host processor. The interface includes a one-wire data line, and a slave processor connected to the data line and including a pull-down circuit for varying voltage on the data line. The slave processor is passive and incapable of sampling data from the data line. The slave processor is programmed to vary voltage on the data line when the data line is energized, to signal at least one data bit.

Data communication interface between host and slave processors

A battery monitoring system and method in accordance with the principles of the present invention, a capacity of interest is determined. This capacity of interest is the useful battery capacity required for an operation of interest; that is, the battery capacity at the discharge rate required for the operation of interest. The operation of interest may be a save-to-disk operation during a battery operated computer shutdown or a shutdown procedure for a personal digital assistant, for example. Given the capacity of interest, alarm settings are determined for a variety of voltage, discharge, and, optionally, temperature conditions. The trip points map, or index, voltage and discharge rate information for one or more discharge rates to one or more capacities of interest. When an indexed battery-voltage/discharge-rate combination that corresponds to the capacity of interest is encountered, an alarm may be set to indicate that, although the present voltage and discharge rates may indicate that there is more or less capacity than required for the critical operation, the capacity of interest (useful energy left at the discharge rate of interest) has been encountered.

Method and apparatus for end of discharge indication based on critical energy requirement

A temperature detector comprising temperature sensing circuitry, calibration circuitry, and power regular circuitry. The temperature sensing circuitry has an output that varies with temperature to create a temperature variation. The calibration circuitry is coupled to receive the output that varies with temperature to create a temperature variation. The calibration circuitry interprets the temperature variation and outputs a valve that represents the temperature. The power supply regulator circuitry coordinates power to the temperature sensing circuitry.

Temperature detector systems and methods

A method of communicating information between a host device and a potentially portable module device which measures thermal accumulation over time via a temperature controlled counter. The temperature controlled counter may operate using substantially Arrhenius' law. The host device communicates with the portable module via a single wire bidirectional data bus. The single wire bus and one-wire communication protocol allows data flow between a host and a plurality of devices connected to the single wire bus. The single wire bus allows for a great versatility of uses for the portable module.

Method of communicating over a single wire bus between a host device and

A metalization layer formed as part of a bump connection/flip chip process for a semiconductor circuit is also used to form a sense resistor or other passive components. The metalization layers normal composition can also be altered so as to change or control the value of the so formed resistor or to improve the temperature stability of the resistor. Other passive components such as capacitors or inductor can also be formed in this layer.

Integral bump technology sense resistor

A digital rheostat or potentiometer which provides both increment and decrement operations from a single input such as a pushbutton. A certain pattern of input actuations will cause the direction of change to reverse. Settings of the potentiometer are stored in nonvolatile memory.

Digital potentiometer

A power regulator for providing a fixed output voltage that is consistent with a reference voltage and independent of a varying power supply, includes a first input connected to a reference voltage generator; a second input adapted to be connected to a varying power supply; two outputs for connection to circuitry such as oscillators; a charge pump; and three transistors. The drain and gate of the first transistor are connected to the charge pump and the source is connected to the reference voltage generator; the gate of the first transistor is coupled to the gates of the second and third transistors; and the sources of the second and third transistors are coupled one of the two outputs.

Power regulator

A temperature detector comprises temperature sensing circuitry calibration circuitry, and power regular circuitry. The temperature sensing circuitry has an output that varies with a temperature to create a temperature variation. The calibration circuitry is coupled to receive the output that varies with temperature to create a temperature variation. The calibration circuitry interprets the temperature variation and outputs a value that represents the temperature. The power supply regulator circuitry coordinates power to the temperature sensing circuitry. Alternate embodiments of the temperature detector comprise temperature sensing circuitry, calibration circuitry, and resolution enhancement circuitry. The temperature sensing circuitry has an output that varies with a temperature to create a temperature variation. The calibration circuitry is coupled to receive the output that varies with temperature to create a temperature variation. The calibration circuitry also interprets the temperature variation and outputs a value that represents the temperature. The value has a resolution. The resolution enhancement circuitry is coupled to the calibration circuitry that enhances the resolution of the value.

A serial-port memory is positioned in a substantially token-shaped body. The substantially token-shaped body has a perimeter and a flange extending from a portion of the perimeter. The serial-port memory comprises a serial port, a scratchpad memory coupled to the serial port, a second memory coupled to the scratchpad memory; and control logic coupled to the serial port and the scratchpad and second memories. The control logic transfers information from the scratchpad memory to the second memory as a block pursuant to a block transfer command received at the serial port. The electronic token has a first electrically conductive surface and a second electrically conductive surface that combines to create a hollow cavity and the serial port, scratchpad memory, second memory, and control logic positioned inside the hollow cavity, the first conductive surface and the second conductive surface can be electrically coupled to transmit electrical signals generated by the serial port, scratchpad memory, second memory, and control logic and to receive externally generated electrical signals. The first electrically conductive surface and the second electrically conductive surface are preferably planar. The control logic includes a cyclic redundancy check generator. Third and fourth memories can be coupled to the scratchpad memory, wherein the control logic transfers information as a block from the scratchpad memory to one of the second, third, and fourth memories pursuant to a block transfer command received at the serial port.

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Dallas, TX, United States of America

Gary V Zanders