Motorola Corporation

Gary V Fay

Stephen P Robb

Lewis E Terry

Keith M Wellnitz

Judith L Sutor

Jeffrey G Mansmann

Bernard W Boland

David H Soo

Steve McKinnis

Alvin Pshaenich

The reverse breakdown voltage of a conventional insulated gate transistor is greatly increased by the addition of a lightly doped layer between the substrate and a buffer layer of the insulated gate transistor. The addition of the lightly doped layer does not increase the on resistance of the device, nor the cut-off time of the device. The lightly doped layer can be provided as an epitaxial layer along with the other epitaxial layers of the insulated gate transistor.

High reverse voltage IGT

MOSFET devices or circuits incorporating an improved substrate temperature sensing element are obtained by forming a PN junction directly on a thin (gate) dielectric region. The temperature sense junction is desirably formed in a poly layer. By mounting it directly on thin (gate) dielectric its thermal response to temperature changes in the substrate is improved while still being electrically isolated from the substrate. It is desirable to provide over-voltage protection elements coupled to the junction to avoid rupture of the underlying thin dielectric. Because the sense diode and all the over-voltage protection devices may be made of poly with junctions perpendicular to the substrate, the structure is particularly compact and simple to fabricate.

Process for forming a semiconductor structure with closely coupled

An improved semiconductor AC switch is described having internal bias generation for the power MOSFET switches and isolated control input. Dual power MOSFETS with substrate diodes are connected in series between source and load. DC gate bias for the MOSFETS is derived from an internal power supply containing energy storage which charges from the line, typically every half cycle. The gates of the power MOSFETS are tied to the internal bias generator through a voltage divider network containing a variable resistance controlled by an optical input signal. The internal energy storage may be a capacitor or solid state battery, preferably a monolithic thick or thin film battery. No transformers or external control bias generators are required and the resulting switch is particularly simple and compact.

Semiconductor AC switch

Semiconductor structure with closely coupled substrate temperature sense

Transformerless semiconductor AC switch having internal biasing means

An integrated circuit switch made with CMOS processes contains a high voltage, high current field effect output transistor. The output transistor serves as a switch and is connected in series with an external load which is to be controlled by the switch. The integrated circuit also contains over current protection circuits and over temperature protection circuits. A circuit also provides fault indications which can be used to determine whether the over current or the over temperature limits were exceeded to shut off the switch.

Low side switch integrated circuit

An integrated circuit power timer having a power field effect transistor and a versatile timing circuit all on one integrated circuit is provided. The integrated circuit has built in thermal and current limit protection and provides a fault indicator in case of an over current or an over temperature condition.

Integrated circuit power timer

A speed control circuit made by using CMOS processes is capable of handling high voltage and high current loads. The output of the speed control circuit is provided by a power field effect transistor. Current sensing means are provided to generate a fault signal in case an over current condition occurs. The junction temperature of the power field effect transistor is also monitored to provide an over temperature condition if the temperature of the junction of the power field effect transistor exceeds a predetermined value. A ramping generator is used to set a latch which controls the operation of the power field effect transistor. A speed control signal is compared against the ramping signal provided by the ramp generator and resets the latch in order to provide speed control.

Integrated circuit speed controller

A semiconductor current regulating and switching apparatus is described wherein an NMOS enhancement mode power transistor is used in the positive lead to regulate the flow of current from a power source to a load. In order to achieve a low resistance on-state for the NMOS power transistor, the control gate must be biased to a voltage which exceeds the positive voltage of the power source. This bias voltage is generated within the apparatus.

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Scottsdale, AZ, United States of America

Gary V Fay