Intel Corporation

Gary Tsao

Hemal Vinodchandra Shah

Sujoy Sen

Anil Vasudevan

Pak-Lung Seto

Linden Cornett

David B Minturn

Anshuman Thakur

Arturo L Arizpe

Victor Lau

Ali S Oztaskin

Nai-Chih Chang

Ashish V Choubal

Harlan Titus Beverly

Tracey L Gustafson

Scott D Hahn

William R Halleck

Gregory Cummings

Christopher T Foulds

Suresh Chemudupati

Greg D Cummings

Ellen M Deleganes

Kiran Vemula

Ankit Parikh

In one embodiment, a method is provided. The method of this embodiment provides storing a packet header at a set of at least one page of memory allocated to storing packet headers, and storing the packet header and a packet payload at a location not in the set of at least one page of memory allocated to storing packet headers.

Header replication in accelerated TCP (transport control protocol) stack processing

Header replication in accelerated TCP (Transport Control Protocol) stack processing

According to one embodiment, an apparatus is disclosed. The apparatus includes a port having a plurality of lanes, a plurality of protocol engines. Each protocol engine is associated with one of the plurality of lanes, and processes tasks to be forwarded to a plurality of remote nodes. The apparatus also includes a first port task scheduler (PTS) to manage the tasks to be forwarded to the one or more of the plurality of protocol engines. The first PTS includes a register to indicate which of the plurality of protocol engines the first PTS is to support.

Method using port task scheduler

Provided are a method, system, and program for managing data transmission from a source to a destination through a network. The destination imposes a window value on the source which limits the quantity of data packets which can be sent from the source to the destination without receiving an acknowledgment of being received by the destination. In one embodiment, the source imposes a second window value, smaller than the destination window value, which limits even further the quantity of data packets which can be sent from the source to the destination without receiving an acknowledgment of being received by the destination. In another embodiment, a plurality of direct memory access connections are established between the source and a plurality of specified memory locations of a plurality of destinations. The source imposes a plurality of message limits, each message limit imposing a separate limit for each direct memory access connection on the quantity of messages sent from the source to the specified memory location of the direct memory access connection associated with the message limit and lacking a message acknowledgment of being received by the destination of the direct memory access connection associated with the message limit.

Method, system, and program for managing data transmission through a network

In accordance with certain other techniques, doorbell information is received. A doorbell structure address is decoded from the doorbell information. A first protection domain identifier is determined from the doorbell structure address. A resource context of a data structure is determined from the doorbell information. The resource context at the doorbell address is read to determine a second protection domain identifier. The first protection domain identifier and the second protection domain identifier are compared to determine whether to update the resource context of the doorbell structure.

Doorbell mechanism using protection domains

An apparatus according to one embodiment may include an integrated circuit. The integrated circuit may include a plurality communication channels. The integrated circuit may be is capable of communicating with at least one remote node external to the integrated circuit, via at least one of the communication channels, in accordance with at least one communication protocol. Each of said plurality of communication channels may provide a communication path between a host system and at least one remote node. The integrated circuit may be further capable of operating each communication channel independently of each other and independently of the host system. Of course, many alternatives, variations, and modifications are possible without departing from this embodiment.

Integrated circuit capable of independently operating a plurality of communication channels

In one embodiment, a method is provided. The method of this embodiment provides determining if a management queue can be created, and if a management queue can be created, allocating virtually contiguous memory to a management queue associated with a device, registering the management queue, and creating a management queue context.

Managing system memory resident device management queues

A method and system for transmitting packets. Packets may be transmitted when a protocol control block is copied from a host processing system to a network protocol offload engine. Message information that contains packet payload addresses may be provided to the network protocol offload engine to generate a plurality of message contexts in the offload engine. With the message contexts, protocol processing may be performed at the offload engine while leaving the packet payload in the host memory. Thus, packet payloads may be transmitted directly from the host memory to a network communication link during transmission of the packets by the offload engine. Other embodiments are also described.

Message context based TCP transmission

Hardware port scheduler (PTS) having register to indicate which of plurality of protocol engines PTS is to support

According to one embodiment, a storage device is disclosed. The storage device includes a port having one or more lanes and a direct memory access (DMA) Descriptor Manager (DM). The DM generates and tracks completion of descriptors. The DM includes a first completion lookup table to track one or more fields of an input/output (I/O) context received at a first lane.

DMA completion processing mechanism

Provided are a method, system, and program for translating virtual addresses of memory locations within pages of different sizes. In one embodiment, a translation entry containing a physical address is stored in a data structure table for each page. Each virtual address includes a page virtual address which identifies the translation entry containing the physical address of the page containing the memory location. The virtual address may be translated to a translation entry index using the size of the page containing the memory location.

Method, system, and program for addressing pages of memory by an I/O device

Provided are techniques for interrupt processing. An Input/Output device determines that an event has occurred. The Input/Output device determines a state of an event data structure. The Input/Output device writes an event entry into the event data structure in response to determining that the event has occurred. After writing the event entry, the Input/Output device determines whether to generate an interrupt or not based on the state of the event data structure. Additionally provided are techniques for interrupt processing in which an I/O device driver determines that an interrupt has occurred. The I/O device driver reads an event entry in an event data structure in response to determining that the interrupt has occurred. The I/O device driver updates a state of a structure state indicator to enable/disable interrupts.

Interrupt system using event data structures

Provided are techniques for interrupt processing. An Input/Output device determines that an event has occurred. The Input/Output device determines a processor identifier and determines an event data structure identifier for an event data structure into which data for the event is stored using the processor identifier. The Input/Output device also determines a vector identifier for an interrupt message vector into which an interrupt message for the event is written. Then, interrupt message data is written to the interrupt message vector to generate an interrupt.

Growing community of inventors

Austin, TX, United States of America

Gary Tsao