Visteon Global Technolgoies, Inc.

Ncr Corporation

Gary Thomas Bastian

Samuel James Guido

Rollie Morris Fisher

Martin G Gravenstein

Robert L Anderson

Raymond Allen Stevens

Kevin Michael Rishavy

Vernon K Schnathorst

A data queue control submodule supporting a host processor and at least one peripheral device. The submodule includes a memory unit with a first memory portion for storing queue commands associated with each peripheral device and a second memory portion for storing peripheral device data. A queue control unit is also included in the submodule for controlling the flow of data between the peripheral devices and the host processor in accordance with the queue control commands. A port interface connects the queue control unit and the peripheral devices in response to a trigger event. The submodule further includes an event controller in communication with the host processor and the port interface for generating event triggers in response to data demands of either the host processor or the other peripheral devices. The present invention is advantageous in that it simplifies the design of each port interface and provides improved flexibility in the queue structure of the overall control system.

Queued port data controller for microprocessor-based engine control applications

An engine control system comprising a host processor in operative communication with a data bus and a plurality of peripheral devices for communicating engine operating parameters. Each of the peripheral devices include a first and second transaction register for storing communication parameters for each of the corresponding plurality of peripheral devices. The control system also includes a queued port rate register (QRR) including a memory unit in operative communication with the plurality of peripheral devices for storing data for transmission to the plurality of peripheral devices in accordance with the first and second transaction registers. The system further includes a peripheral counter in operative communication with each of the plurality of peripheral devices. The peripheral counter is adapted to interrogate each of the plurality of peripheral devices and, when data has been written to one of the peripheral devices, update the peripheral device according to the memory unit data.

An electronic circuit for regulating the entry of new data into a static synchronous register comprising a bank of D type, master-slave flip-flops. The circuit selectively passes the first phase of a two-phase, nonoverlapping clock signal used for synchronization and control of the data. A bootstrap operated, series pass, transistor configuration couples the first phase signal to the electrode actuating the master stage of each flip-flop. With provisions for the series pass transistor to transition into a conductive state prior to the onset of the first phase signal, the circuit ensures substantial replication of the first phase signal characteristics in terms of both time and amplitude.

High speed write control for synchronous registers

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Colorado Springs, CO, United States of America

Gary Thomas Bastian