International Business Machines Corporation

Gary T Hendrickson

David William Boerstler

Edward B Eichelberger

Charles B Winn

Anthony Correale, Jr

Electronic device holder

A level shifting circuit operating at low power with minimal signal delays. The circuit employs high capacitance diodes to shift signals from a first signal level to a second higher or lower signal level. The capacitance is obtained by either providing a discrete capacitor shunt across the diode or by using diode connected transistors. Diode connected transistors are biased to provide the necessary capacitance. A pair of high capacitance diode level shifters is used as a differential pair level shifter by connecting the reference resistors to a common reference potential.

Speed enhanced level shifting circuit utilizing diode capacitance

A small and efficient control circuit for a compensated CMOS off-chip driver and a driver circuit incorporating the control circuit. The control circuit uses an exclusive OR gate as a phase detector to determine the phase difference between a system clock and a delayed version of the system clock. An RC filter smooths the output of the exclusive OR gate to produce a voltage proportional to the delay introduced in the CMOS circuitry by environmental and process variables. The voltage from the RC filter is used as a control voltage to control the effective channel width of the effective pull-down device of the off-chip driver circuit. An off-chip driver using the control circuit is used in the I/O unit of a CMOS integrated circuit chip.

Process insensitive off-chip driver

A low signal margin detect circuit for detecting reduced signal levels in differential current switch (DCS) or current switch emitter follower (CSEF) circuits. The circuit is connected to the outputs of a DCS circuit or to the output of a current switch emitter follower circuit and a reference voltage. A signal difference between the inputs is determined and, if less than an established amount, an error signal is generated. The detect circuit is enabled by a TESTBIAS signal. Two error signals are developed, ERRORX and ERRORY, which can be dotted with the error signals from adjacent circuits in the X and Y directions. This enables detection of the failing circuit through the use of appropriate error signal detection devices.

Low signal margin detect circuit

An output stage device for an enhanced differential current switch. The output stage receives a differential signal pair from a prior logic stage and must shift the output signals to the levels necessary for the next stage. The output stage has a differential pair of emitter followers that are capacitively cross coupled. Capacitors couple the collector of a first transistor to the emitter of the second. The capacitors can be formed from forward biased diodes or transistors. The result is a more rapid falling output transition while reducing power requirements.

Capacitively cross-coupled DCS emitter-follower output stage

A compensating upshift circuit providing low signal degradation and operating at high speed and at low power. Capacitor shunted diodes cross-couple the collectors and bases of two transistors. The cross-coupling eliminates signal swing degradation in the upshift circuit and controls current through the two collector resistors. Equalized collector resistor current eliminates signal swing degradation while providing an upshift circuit with short delays. The capacitor shunted diodes can be replaced by diode connected transistors configured to provide the necessary collector-base capacitance.

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Kingston, NY, United States of America

Gary T Hendrickson