Maxim Integrated Products, Inc.

National Semiconductor Corporation

Gary Steven Murdock

Prem Ramachandran Nayar

Paul Fuller

Yan Yan

Systems and methods provide secure, end-to-end high-speed data encoding and communication. In certain embodiments, this is accomplished by modifying a header portion of a data packet received from a first device and complying with a one Mobile Industry Processor Interface (MIPI) protocol to create a modified data packet that complies with a faster MIPI protocol. The header portion of the modified data packet is validated during a tunnel mode operation using an error detection process to validate the modified data packet, which can then be securely transmitted to a second device that complies with the faster MIPI protocol.

MIPI translation in gigabit multimedia serial link

MIPI translation in GMSL tunnel mode

Self-clocked two-level differential signaling methods and apparatus assuring both clock synchronization and ease of recovery of transmitted data. In accordance with the method, the data is encoded differentially on a differential signal that changes polarity at the end of each bit time. This allows clock recovery at the receiver simply by detection of the polarity change. The data is encoded, bit by bit, as exceeding a predetermined magnitude for a bit of a given state and as not exceeding the predetermined magnitude for the opposite state. Consequently data recovery is by way of a simple signal magnitude detection during a bit time, such as by a detection of signal magnitude a predetermined time. The apparatus does not require a phase locked loop in the receiver, thereby saving power and time to obtain synchronization. The method is conducive to varying bit time or duration, thereby reducing the peaks in the EMI radiation.

Self-clocked two-level differential signaling methods and apparatus

A highly efficient bit encoder and a method related thereto are provided. The bit encoder transmit DC-balanced digital signals over a transmission line. To provide a DC-balanced signal, an input word's single-word disparity (SWD) value is compared to a running word disparity (RWD) value retrieved from a memory register. The RWD value indicates the cumulative DC-imbalance on the transmission line. If the disparity relationship of the SWD and the RWD satisfy a set of predefined rules, the input word is inverted to thereby offset the RWD. An inversion bit is appended to the digital input word to provide an output digital word to indicate to a receiver whether the transmitted output word is inverted to thereby permit recovery of the original system word. In one application, the DC-balanced signal transmits alternately control words and data words. A clock signal is transmitted on a separate clock transmission line to provide a clock signal for timing purposes and an embedded control signal indicating control or data mode.

Apparatus and method for providing direct current balanced code

A transceiver interface device in accordance with the present invention includes features which allow the transceiver to be switched for operation in either a differential or a single-ended mode. First, the output levels of the transceiver's differential line driver are switchable between TTL levels and non-TTL levels with small differential swings. Second, the transceiver's differential receiver is switchable between a differential threshold and a single-ended TTL threshold. Third, while in differential mode, both outputs of the driver may be placed in the high impedance state or active at the same time, but it is also possible to switch to a single-ended mode in which one driver output is in the high impedance state while the other can be switched between being active or being in the high impedance state. Fourth, the transceiver uses the SCSI standard DIFFSENS pin or driver enable signal for switching between differential mode and single-ended mode operation.

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San Jose, CA, United States of America

Gary Steven Murdock