International Business Machines Corporation

Other

Gary Stephen Ditlow

Paul David Kartschoke

Bruce Martin Fleischer

Terry I Chappell

Barbara A Chappell

David J Widiger

Barry Lee Dorfman

Michael P Beakes

Vinod Narayanan

Ghavam G Shahidi

Steven Frederick Oakland

Robert Alan Philhower

Chih-Liang Chen

Kenneth J Shaw

Dac C Pham

George Anthony Halasz

A computer-based method automatically synthesizes, optimizes and compiles high performance control logic using SRCMOS LOGIC ARRAY MACROS, abbreviated as SLAMs. The method includes a series of steps that transform a high level design description into a set of SLAMs, and includes the steps of partitioning the logic description of a unit into blocks that are suitable for mapping to a target SLAM structure; mapping each logic partition to the target SLAM structure; creating a configuration and relative layout for the internal structure for each SLAM; creating an external description for each SLAM, each description being of sufficient detail to carry out physical design and integration of the unit which contains the SLAM; assembling the partitions implemented as SLAMs with other macros in the unit; resolving interface conflicts between the different macros by selecting appropriate signal interfaces for various SLAMs; repeatedly changing the external specifications of the various SLAMs; analyzing the performance of the unit; automatically compiling the schematic and layout of each SLAM within the unit based on the configuration and relative layout; and assembling the macros and analyzing the design for design rule violations.

Method and apparatus for synthesizing and optimizing control logic based

A logic circuit family implements self-resetting CMOS logic array macros (SLAMs) which include a plurality of inputs to which a plurality of data input signals can be applied; a plurality of input buffers coupled to receive the input signals from the inputs; a NOR circuit coupled to receive the outputs of the input buffers and a pulsed logic timing signal synchronized within a predefined window with the arrival of the data input signals; an output buffer coupled to receive the output of the NOR circuit; and an output at which a data output signal is produced, with the output signal being a logical NOR of the data input signals; and with each of the NOR circuit, the plurality of input buffers, and the output buffer optionally having a separate reset input to reset it to a standby state. The SLAMs address the very high pressure on the performance of both control logic and control logic design systems. The distinguishing features of SLAMs are uniquely combined to allow the automated design, from a logic description and interface specifications, of a complete macro satisfying predetermined design guidelines.

Compiled self-resetting CMOS logic array macros

A PLA whose slowest product terms are located as close as possible to the true/complement generators or input buffers. The associated input buffers and product terms are partitioned into two or more sections. A modified gap cell recombines the product terms before propagating the signal into an array.

Programmable logic array and method for its design using a three step

An apparatus for redirecting late-entering PLA input signals to avoid holding up the entire PLA while the late-entering signals are processed, and a method for designing the same.

PLA late signal circuitry using a specialized gap cell and PLA late

A reduced power programmable logic array is disclosed. The circuit includes an AND array, coupled through product term lines to an output OR array. Pull-up devices in the OR array are gated to one of the active product term lines. Also disclosed is method for choosing a product term line for gating pull-up devices such that power consumption in the pull-up devices is minimized.

Reduced power PLA

Method of power reduction in pla's

A pulsed static CMOS circuit. Improved static CMOS circuit speed is achieved without using a clock scheme like that in dynamic CMOS circuits. The disclosed circuit family is a pulsed static CMOS circuit which makes only a single transition during evaluation. The circuit is reset to a predetermined state by an input pattern, which is in favor of the faster switching direction of the static CMOS.

Pulsed static CMOS circuit

A programmable logic array (PLA) is provided with a decoder at the input. Each product term line of the PLA has an associated power switch that is controlled by an output of the decoder. Only a portion of the PLA that includes the product term lines activated for a particular operation is powered up for that operation, thus minimizing power consumption.

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Garrison, NY, United States of America

Gary Stephen Ditlow