Burr-brown Corporation

Texas Instruments Corporation

Gary S Gibson

Sanjeev Manandhar

First and second transconductance amplifier input stages having first and second gain characteristics, respectively, are combined. The resulting combined input stage has a third gain characteristic with a linear range that is larger than a linear range of either of the first and second gain characteristics.

Combined input stage for transconductance amplifier having gain linearity over increased input voltage range

A circuit provides at least partial thermal shutdown of an integrated circuit chip including a functional circuit (7) in response to detection of a hot spot in a first area of the chip. First (Q1) and second (Q3) transistors in a second area (3) of the chip are located a first distance (10) from the second area of the chip, and third (Q4) and fourth (Q2) transistors in a third area (4) of the chip are located a second distance (11) substantially greater than the first distance from the first area. The functional circuit (7) dissipates power in the first area, causing a temperature in the hot spot to rise to approximately a first temperature T3 and causing the temperature of the first and second transistors to be a second temperature T2 and causing the temperature of the third and fourth transistors to be a third temperature T1. The first, second, third and fourth transistors are operated to in effect extrapolate between the second T2 and third T1 temperatures to produce a current (IOUT) proportional to the difference between the second T2 and third T1 temperature, and hence representative of the first temperature T3. At least a portion of the functional circuit turned off to reduce the temperature of the first region has a value that exceeds a predetermined maximum value.

Thermal shutdown circuit and method for sensing thermal gradients to

A push-pull output stage includes an NPN pull-up transistor (Q6) and an NPN pull-down transistor (Q7) connected to an output. A compensation capacitor 17 is coupled between the collector and base of the pull-down transistor. A differential input stage includes emitter-coupled first (Q2) and second (Q3) NPN input transistors each coupled by a degeneration resistor to a constant current source. A base of the first NPN input transistor (Q2) is coupled to receive a shifted input voltage (V.sub.IN), and a base of the second NPN input transistor is coupled to the output conductor (3). The collectors of the first (Q2) and second (Q3) input transistors are connected to the sources of a folded cascode circuit including first (J1) and second (J2) cascode P-channel JFETs, respectively, the drains of which are connected to a current mirror output transistor (Q5) and a current mirror control transistor (Q4), respectively. The collector of the current mirror output transistor (Q5) is connected to the base of the pull-down transistor (Q7). The voltage gain of the output stage is determined primarily by the degeneration resistors and the compensation capacitor and hence is quite independent of the load impedance, and therefore provides stable circuit operation. A shoot-through current limiting circuit includes a capacitor and a resistor coupled between the input (V.sub.IN) and the base and collector of the current mirror control transistor (Q4).

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Tucson, AZ, United States of America

Gary S Gibson