International Business Machines Corporation

Utopus Insights, Inc.

Gary S Ditlow

Daria Rose Dooling

Ralph James Williams

Jinjun Xiong

David Erin Moran

Robert K Montoye

Dung Tien Phan

Thomas Wood Wilkins

Leland Chang

Brian L Ji

Clifford A Pickover

Brian Paul Gaucher

Stephen D Thomas

Richard L Moore

Luis Alfonso Lastras-Montano

Matthew Joseph Breitwisch

Michele M Franceschini

Stephen Victor Kosonocky

Mark Alan Lavin

Ruchir Puri

Bipin Rajendran

Gustavo Enrique Tellez

Fook-Luen Heng

William C Leipold

Salvatore Nicholas Storino

Timothy G Dunham

Soroush Abbaspour

Chandramouli V Kashyap

Jung H Yoon

Daniel Lawrence Ostapko

Brian Chan Monwai

Robert A Proctor

J Adam Butts

An exemplary method includes solving on a computing system an optimal power flow formulation for a plurality of generators in a power system. The solving includes computing using multi-threaded parallelism a plurality of constraints for the formulation, computing using multi-threaded parallelism a plurality of Jacobian functions of the constraints, and computing using multi-threaded parallelism a Hessian of Lagrangian functions. The method further includes outputting results of the solving, wherein the results comprise values of generation levels for the plurality of generators. Apparatus and program products are also disclosed.

Parallel technique for computing problem functions in solving optimal power flow

A method includes determining whether transformer phases should be permuted. The method includes, responsive to a determination that the transformer phases should be permuted, permuting the transformer phases, based on historical aging information of transformer input phases, to cause transformer input phases with higher ages to be connected to transformer output phases with lower output loads and transformer input phases with lower ages to be connected to transformer output phases with higher output loads. Multiple apparatus and program products are also disclosed.

Transformer phase permutation causing more uniform transformer phase aging and general switching network suitable for same

A method, system and apparatus for operating an energy-using device are disclosed. Current data related to operation of the energy-using device is received at a remote device. An operating specification for the energy-using device is received at the remote device from a database. A recommended setting of the energy-using device is determined from the current data and the operating specification. The remote device communicates the recommended setting to the energy-using device. A control unit at the energy-using device receives the recommended setting and implements the recommended setting at the energy-using device.

Interactive energy device for environmental stewardship

Resistive memories having a not-and (NAND) structure including a resistive memory cell. The resistive memory cell includes a resistive memory element for storing a resistance value and a memory element access device for controlling access to the resistive memory element. The memory element access device is connected in parallel to the resistive memory element.

Resistive memory devices having a not-and (NAND) structure

A memory device for performing logical operations on two or more input variables includes a match line and first and second memory cells. The first and second memory cells collectively include a first, second, third and fourth memory element. The first, second, third and fourth memory elements may have either a first value or a second value programmed therein and wherein the first, second, third and fourth memory elements are programmed to either the high or low resistive values based on a particular logic function to be performed.

Content addressable memory array programmed to perform logic operations

A memory device for storing one or more addresses includes a match line and first and second memory cells that form a 2-bit memory cell. Each memory cell includes two memory elements coupled to a match line and selection lines coupled thereto. The selection lines provide a signal representative of a logical combination of at least two different inputs.

Content addressable memory array

A memory system includes a content addressable memory (CAM) including a plurality of match lines, each match line having a plurality of memory cells coupled thereto. The system also includes a match detector coupled to the CAM and a reference match line having a plurality of reference memory cells coupled thereto, the reference memory cells being of the same type and the memory cells. The system also includes a match line sensor coupled to the reference match line and the match detector that determines a characteristic of the reference match line and provides a timing signal to the match detector based on the characteristic.

Content addressable memory reference clock

An embodiment of the invention provides a method of separating an early clock pulse and a late clock pulse into two different latches, wherein the early clock pulse is generated through a bit line. In response to the early clock pulse rising, a first data waveform is sent to a fourth data waveform. In response to a third data waveform rising, an early precharge is turned off. In response to the turning off of the early precharge and in response to a fifth data waveform dropping, an eighth data waveform rises if the first data waveform has a value of 1. In response to a sixth data waveform rising, a first pulse latch is opened.

SerDes double rate bitline with interlock to block precharge capture

A method and structure for determining a listing of host processors on a network to perform a parallel application, including determining a listing of all possible hosts on the network for performing the parallel application, determining for each of the possible hosts a current capacity and a current utilization, calculating for each of the possible hosts a difference between the current capacity and the current utilization, and selecting from the listing of all possible hosts a listing of hosts based on sorting the calculated differences.

Method and apparatus to manage multi-computer supply based on an economic model

A circuit incorporating a current starved ring oscillator is coupled to a power gate switch in an integrated circuit. The circuit incorporating the current starved ring oscillator amplifies a voltage difference between a virtual ground associated with the power gate switch and ground, and converts the difference to a frequency. Digital logic monitors the output of the ring oscillator using a counter and a reference clock. Control circuitry controls operation of the integrated circuit in dependence on the monitored conditions associated with the power gate switch. A method monitors a virtual ground voltage across a power gate switch in an integrated circuit; and controls operation of the integrated circuit in dependence on the monitored virtual ground voltage.

Methods and apparatus for monitoring power gating circuitry and for controlling circuit operations in dependence on monitored power gating conditions

Method and apparatus to manage multi-computer supply using a model based on an economic model of supply and cost of supply

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Yorktown Heights, NY, United States of America

Gary S Ditlow