USA As Represented by Secretary of the Navy

US Government As Represented by the Secretary of the Army

Gary S Borgen

Christian Lauritz Houlberg

James L Sullivan

Bradford S Davis

Thomas E Harkins

Richard James Busse

David J Hepner

Michael S L Hollis

William P D'Amico

Jeffrey J Pacl

David Escobar Marron

Peter C Muller

Lawrence W Burke

An encryptor/decryptor which receives a continuous parallel data stream either in a single-ended TTL or a Low Voltage Differential Signaling format. The encryptor/decryptor selectively encrypts or decrypts the incoming data stream, using an LVDS encryptor/decryptor and then outputs the data stream in either a LVDS or TTL parallel format.

Parallel encryptor and decryptor

A PCM encoder which receives asynchronous serial data and incorporating the serial data and eight channels of analog data into a PCM data stream. The encoder includes a microprocessor which processes the serial data provided in eight bit digital words and the analog data which the microprocessor converts to twelve bit digital words. The encoder also has a programmable gate array which receives six bits of data during each transfer of data from the microprocessor to the gate array. The gate array for the PCM encoder also receives a Frame Sync, and then processes the data to provide a data stream containing NRZL data and Bi Phase data.

Miniaturized pulse code modulation encoder

A method for storing a crypto key and an associated checkword of the crypto key stored in a non-volatile memory within a micrcontroller and then providing the crypto key and associated checkword to an encryption device. The method next loads the crypto key and associated checkword into the encryption device.

Method for providing a crypto key and checkword to an encryption device

A method using a Non-Volatile Memory circuit which operates as an interface between a key loader and an encryption device in a missile's telemetry system. The method includes a step for storing a crypto key and an associated check word and a backup crypto key and check word in the EEPROM of a microcontroller, and a step for indicating the status of a load of the crypto key in the microcontroller as well as a step for indicating the status of an erase of the crypto key from the microcontroller. The method also includes a step for turning off the missile's transmitter when a key load occurs to prevents transmission of the crypto key and its corresponding check word. The method further includes a step for erasing the crypto key and its associated check word from an EEPROM within the microcontroller upon a missile launch.

Method which uses a non-volatile memory to store a crypto key and a check word for an encryption device

A Non-Volatile Memory circuit operating as an interface between a key loader and an encryption device. The Non-Volatile Memory circuit includes a microcontroller which stores a crypto key and checkword and a backup crypto key and checkword. The microcontroller is connected to the telemeter transmitter for a missile allowing the micrcontroller to turn off the transmitter during a key load which prevents transmission of the crypto key and checkword. When the microcontroller completes a load of the crypto key to the encryption device and upon a launch of the missile, software within the microcontroller erases the crypto key and checkword from an internal EEPROM. This prevents an enemy force from retrieving the crypto key and its corresponding checkword from the missile after launch.

Non-volatile memory for use with an encryption device

A programmable pulse code modulation encoder comprises a programmable controller arranged to receive a digital signal input and a plurality of parallel analog signal inputs. The said programmable controller is arranged to digitize the parallel analog signal inputs and modulate them with the digital signal input. A system clock is included to provide clock signals. A counter circuit is connected to the programmable controller to provide interrupt signals under the control of the system clock. A shift register is connected to the programmable controller to receive modulated parallel digital signals corresponding to the parallel analog signal inputs to the programmable controller. The shift register is also connected to the counter and is arranged to function as a parallel to serial converter to provide a serial data stream output at an output terminal of the shift register.

Pulse code modulation encoder for data acquisition

A system which is packaged within a projectile fuze body and obtains data relative to the projectile during a launch. Sensors are provided which obtain in-bore data as well as in-flight data. The in-bore data is recorded at a fast rate during in-bore travel of the projectile and is read out, continuously, at a slower rate during in-flight travel. Both in-bore data and in-flight data are encoded and transmitted to a ground station for analysis.

Aeroballistic diagnostic system

A three phase one kilo-hertz power supply which generates a three phase pr single having a line to line voltage of 22 VRMS. The power supply is adapted to operate with an input power source of 90 to 264 VRMS having a frequency range of 50 hertz to 1000 hertz. The power supply comprises three electrically programmable read only memories with each memory containing 1024 point, eight bit binary data representations for generating one complete cycle of a sine wave. Addressing is provided by a binary counter which also generates a 1.024 MHz sampling signal for use by three digital-to-analog converters. Each digital-to-analog converter converts the 1024 point, eight bit binary data representations to a sine wave having a frequency of one kilo-hertz resulting in three sine waves which are phase separated by 120 degrees. Each sine wave is amplified and filtered by an anti-aliasing filter which attenuates selected undesirable frequencies from the sine wave eliminating any distortion effects in the sine wave signal caused by digital to analog sampling.

Three phase one kilo-hertz power supply

A memory card drive which is compatible with MS-DOS computer systems as w as other computers which do not use MS-DOS as the operating system. The memory card drive comprises an embedded server which is a bridge between a client computer and a pair of memory cards allowing for communication and data transfer between the client computer and the memory cards. The server includes an ethernet interface which connects the server to ethernet bus which is connected to the client computer. The server has a memory card interface module which allows the client computer to communicate with the memory cards and thereby transfer data to the memory cards and retrieve data from the memory cards. The server also includes an embedded computer which enables and controls the functions and operation of the memory card interface and ethernet interface using a computer software program. The embedded computer has a two megabyte hard drive which has the computer software program stored therein.

Programmable stand-alone drive apparatus for interfacing a host computer

An electronics circuit for digitizing an analog audio data signal into a ital equivalent signal and then introducing digitized nyquist dither data into the digital equivalent signal to substantially eliminate the need for removing the nyquist dither data from the digital equivalent signal prior to its conversion to an analog signal which is a substantial replica of the incoming analog audio or like data signal. The electronics circuit comprises a first pseudo-random number generator which generates a series of digitized nyquist dither bits for addition to the digital equivalent signal. The digitized nyquist dither bits are, in turn, provided by an external computer using a computer program which first generates a pseudo-random sequence of positive integers over a first predetermined range. The computer program implements a high pass filter which processes the pseudo-random sequence of positive integers to generate the digitized nyquist dither bits for use by the programmed read only memory as the dither bits to be added to the digital equivalent signal. A binary adder adds the digitized nyquist dither bits to the digital equivalent signal and then provides the resulting digital equivalent signal with dither to a first clipping circuit. The first clipping circuit clips the digital equivalent signal with dither to a maximum binary value having every bit at the logic one state and a minimum binary value having every bit at the logic zero state.

Digital circuit for the introduction of dither into an analog signal

An electronics circuit for accurately digitizing an analog audio, video or ike data signal into a fourteen bit digital equivalent signal/words having thirteen data bits and a sign bit and then introducing a dither component into the digital equivalent signal. The circuit includes a first Electrical Erasable Programmed Read Only Memory which generates a dither component to be added to a selected, five, six, seven or eight bits of each fourteen bit digital equivalent sample. The circuit also includes an automatic gain control circuit and a data selector circuit which, in combination, select the five, six, seven or eight data bits of the thirteen data bits of each digital equivalent sample to supply to a binary adder. The binary adder then adds the dither component to the selected data bits of each digital equivalent sample. The five, six, seven or eight selected bits of each fourteen bit sample provide optimum video, audio or like information for the sample.

An electronics circuit for accurately digitizing an analog audio, video or ike data signal into a fourteen bit digital equivalent signal/words having thirteen data bits and a sign bit and then introducing a dither component into the digital equivalent signal. A Read Only Memory which generates an eight bit dither component to be added to a selected eight bits of each fourteen bit digital equivalent sample. The combination of an automatic gain control circuit and a data selector circuit is provided which selects eight of the thirteen data bits of each sample to supply to a binary adder which adds the dither component to each sample. The eight selected bits of each thirteen bit data sample provide optimum video, audio or like information for the sample. A binary adder is also provided to add the dither component to each bit sample before providing the resultant signal to a missile's telemetry system.

An electronics circuit for digitizing an analog audio or like data signal to a six bit digital equivalent signal and then introducing a dither component into the digital equivalent signal. The electronics circuit includes an Erasable Programmed Read Only Memory (EPROM) which generates a six bit dither component to be added to the digital equivalent signal. A binary adder adds a dither bit to each of the six bits of the digital equivalent signal and then provides a three bit equivalent digital signal. The three bit equivalent digital signal is then written in parallel into a first storage register, while one bit of the three bit digital equivalent signal is written into a second storage register. When a fuze active signal, which is input to the present invention, is a logic zero the first register is enabled for a read operation allowing the three bit equivalent digital data to be read from the first register to a parallel to serial converter which converts the data to a serial three bit digital format. When the fuze activate signal is a logic one the second register is enabled for a read operation allowing the one bit equivalent digital data to be read from the second register to the parallel to serial converter which converts the data to a serial one bit digital format.

A digital audio signal processing circuit for eliminating the amplitude and phase components of logic induced modulation from a left right clock signal, a bit clock signal and digital data bits generated by a digital signal processor within a compact disk player. The digital audio signal processing circuit includes a trio of optical couplers for removing the amplitude component of logic induced modulation from the left right clock signal, the bit clock signal and the digital data bits; a clock circuit for generating a system clock signal and a trio of D Flip-Flops for removing the phase component of logic induced modulation from the left right clock signal, the bit clock signal and the digital data bits and a digital to analog converter for separating the data bits into left channel data bits and right channel data bits and for converting the left channel data bits into a first analog signal and the right channel data bits into a second analog signal for use by speakers or the like to provide stereo sound. An isolated power supply provides both analog and digital voltages to the electronic elements of digital audio signal processing circuit.

Digital audio signal processing circuit

A nonvolatile memory system is disclosed which will store a key or digital word for a period of time of approximately three years with minimum power consumption. The nonvolatile memory system includes a nonvolatile static random access memory for receiving and storing a key word from a loader, and a nonvolatile memory sequence control circuit which provides logic signals for controlling read and write operations of the nonvolatile static RAM, as well as logic signals to allow for transfer or down loading of the key word from the loader to the RAM. In addition, the nonvolatile memory sequence control circuit provides logic signals to interface with an encryption device which allows the key word to be transferrred or up loaded from the nonvolatile static RAM to the encryption device and logic signals for storing the key word in a nonvolatile electrically erasable programmable read only memory (PROM) and then bringing the nonvolatile static RAM to a low power standby state. An erasable PROM (EPROM) is used to control the sequencing of operations within the nonvolatile static RAM with addressing for the EPROM being provided by the nonvolatile memory sequence control circuit. The EPROM and the nonvolatile memory sequence control circuit may be also brought to a low power standby state by a power control signal provided by the memory sequence control circuit.

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Camarillo, CA, United States of America

Gary S Borgen