Arm Limited

Gary Robert Waggoner

Robert Campbell Aitken

Yew Keong Chong

Gus Wai-Yan Yeung

Paul Stanley Hughes

Paul Darren Hoxey

Dipesh Ishwerbhai Patel

Faisal Ramzan Ali Khoja

Sauro Landini

Ramamurti Chandramouli

An integrated circuit and method for testing memory on the integrated circuit are provided. The integrated circuit has processing logic for performing data processing operations on data, and a plurality of memory units for storing data for access by the processing logic. Further, memory test logic is provided to perform a sequence of tests in order to seek to detect memory defects in the memory units. The memory test logic comprises a plurality of test wrapper units, each test wrapper unit associated with one of the memory units and being operable to execute tests on the associated memory unit, and a test controller for controlling performance of the sequence of tests by communicating with each of the test wrapper units to provide test data defining each test to be executed by that test wrapper unit. Further, a first communication link is provided for connecting each of the test wrapper units directly to the test controller, and a second communication link is provided for connecting each test wrapper unit in an ordered sequence with the test controller. When controlling performance of the sequence of tests, the test controller provides first test data via the first communication link and second test data via the second communication link. It has been found that such an approach provides a particularly efficient and flexible technique for performing BIST functions within the integrated circuit.

Integrated circuit and method for testing memory on the integrated circuit

The application discloses an integrated circuit comprising: circuitry; a fusebox for storing an array of data identifying faulty elements within said circuitry; at least one fusebox controller for repairing said faulty elements in said circuitry in response to data received from said fusebox; a data communication path linking said fusebox controller with said fusebox; wherein said data stored in said fusebox is compacted data and said at least one fusebox controller comprises a data expander for expanding said compacted data received from said fusebox via said data communication path prior to repairing any faulty elements in said circuitry.

Method and apparatus for handling fuse data for repairing faulty elements within an IC

A memory is disclosed comprising: a storage array for storing data; and access circuitry for transmitting data to and from the storage array. The access circuitry forms a data path for inputting and outputting data to the storage array. The access circuitry comprises a latch configured to latch in response to a first phase of a first clock signal and a further latch configured to latch in response to a second phase of a second clock signal, the further latch comprises an output latch for outputting the data from the storage array, and the first and second clock signals are synchronized with each other. The memory further comprises: a multiplexer, a scan input and a scan enable input, the multiplexer being responsive to an asserted scan enable signal at the scan enable input to form a scan path comprising the latch and the further latch connected together to form a master slave flip flop, such that scan data input at the scan input passes through the master slave flip flop and not through the storage array while the scan enable signal is asserted and is output by the output latch.

Supporting scan functions within memories

An integrated circuitincludes a plurality of circuit blockseach having an associated serial scan chain loopwhich extends from a converter, to the circuit blockin question and then back to the converter. Multiplexing circuitryassociated with each serial scan chain loopis used to either include that serial scan chain loopin a combined serial scan chain or to bypass that serial scan chain loop. The circuit blocksmay be bypassed in this way if they are defective or if they are powered-down.

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San Jose, CA, United States of America

Gary Robert Waggoner