Sun Microsystems, Inc.

Gary R Oblock

Marc R Tremblay

David R Wallace

Nik Shaylor

Jeffrey M W Chan

The present invention provides a method and an apparatus for translating a virtual address to a physical address in a computer system. The system receives a virtual address during an execution or a fetch of a program instruction. The system determines if the virtual address is in an upper portion or a lower portion of a virtual address space. If the virtual address is in the lower portion of the virtual address space, the system adds the virtual address to a first base address to produce the physical address. The system also compares the virtual address against an upper bound. If the virtual address has a larger value than the upper bound, the system indicates an illegal access. If the virtual address is in the upper portion of the virtual address space, the system adds the virtual address to a second base address to produce the physical address. The system also compares the virtual address against a lower bound. If the virtual address has a lower value than the lower bound, the system indicates that the access is illegal. Thus, the system provides protection from illegal memory accesses. According to one aspect of the present invention, the system determines if the virtual address falls within portion of the virtual address space that is protected from write accesses. If so, the system disallows write accesses to the virtual address. Thus, the present invention dispenses with paging and reduces the virtual-to-physical address translation process to a simple addition operation. This leads to faster processor clock speeds, and can greatly reduce the cost of designing and fabricating a computer system.

Method and apparatus for a high-performance embedded memory management unit

A method and apparatus is provided for determining and resolving cache conflicts among data arrays that are stored in the main memory of a computer system in which the main memory is coupled with a memory cache that is coupled in turn with a microprocessor. According to the method of the invention, a cache shape vector that characterizes the size and dimension of the cache is determined under computer control. A determination of at least one cache conflict among the arrays stored in the main memory is then determined, in addition to the conflict region in the cache for the conflicting arrays. A padding value is then determined for the arrays stored in the main memory, and the memory locations of the arrays are adjusted in accordance with the padding value to prevent cache conflicts when the data from the conflicting arrays is transferred from the main memory into the cache.

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Mountain View, CA, United States of America

Gary R Oblock