Xilinx, Inc.

Gary R Lawman

Joseph D Linoff

James L Burnham

Robert W Wells

Stephen M Trimberger

Bernard J New

Austin H Lesea

Robert O Conn

Steven Hennick Kelem

Christopher H Kingsley

Chidamber R Kulkarni

Stephen L Wasson

A method and apparatus that uses device defects as an identifier. Data is written to memory of an integrated circuit. Defects are identified based upon the writing of the data. An identifier for the IC is then derived using the identification of the defects.

Method and apparatus using device defects as an identifier

A tunable clock distribution system is used to minimize the power dissipation of a clock distribution network in an integrated circuit. The tunable clock distribution system provides a tunable inductance on the clock distribution network to adjust a resonant frequency in the tunable clock distribution system. The inductance is tuned so that the resonant frequency of the tunable clock distribution system approaches the frequency of the clock signal on the clock distribution network. As the resonant frequency of the tunable clock distribution system approaches the frequency of the clock signal, the power dissipation of the clock distribution network decreases. Some embodiments also provide a tunable capacitance on the clock distribution network to adjust the resonant frequency of the tunable clock distribution system.

Tunable clock distribution system for reducing power dissipation

A field programmable gate array (FPGA) is provided that can selectively accept or reject selected software (macros). Specifically, configuration data for the FPGA is passed through a configuration port to a decoder. The decoder processes the configuration data to detect locked macros. If a locked macro is detected, the decoder attempts to unlock the locked macro using one or more keys stored in a key table of the FGPA. If an appropriate key is in the key table, the decoder unlocks the locked macro to configure the FPGA. The keys can be pre-programmed into the FGPA by the macro vendor. If configuration data containing a locked macro is used with an FPGA without the appropriate key, configuration of the FPGA fails.

FPGA customizable to accept selected macros

A method is provided for configuring an FPGA to accept or reject selected software (macros). Specifically, if an end user desires to use a locked macro from a first macro vendor a locked macro from a second macro vendor in the same FPGA, a key manager prepares a keyed FPGA for the end user by pre-programming an FPGA with a first key, which is configured to unlock the first locked macro, and a second key, which is configured to unlock the second locked macro. The key manager obtains the first key from the first macro vendor and the second key from the second macro vendor. The keys are stored in a key table of the FPGA that is write-only from outside the FPGA. The end user pays a fee to the key manager for the keyed macro, but is not given access to the keys. The key manager apportions the fee from the end user and distributes appropriate licensing fees to the first macro vendor and the second macro vendor.

Methods to securely configure an FPGA to accept selected macros

A method of specifying design parameters is provided for configuring circuits for programmable ICs. A design database describing a circuit is displayed in table-based format on a computer screen display. The design database may include a memory map including data to be placed in bit-storage space in the target programmable IC. This design database requires no schematics or HDL description of the circuit, even for complicated application-specific circuits. The desired parameters are entered by the user, typically using toggle buttons, pull-down menus, or keyboard entry. The selected parameters are then entered into the design database, thereby configuring the design database in accordance with the selected parameters. Next, the design database is transmitted over a data communications link such as the internet to a second computer, on which the compilation software resides. The design is then compiled and the resulting netlist is transmitted back to the originating computer. In one embodiment, a schematic symbol or HDL instantiation is also generated by the second computer, and transmitted back to the originating computer.

Method for configuring circuits over a data communications link

A method is provided for securely configuring an FPGA with macros. Specifically, if an end user desires to use a macro from a macro vendor, the end user creates a marked design file containing a macro marker rather than the actual macro. The marked design file is converted into configuration data by a macro manager. Specifically, the macro manager obtains the macro from the macro vendor and replaces the macro marker with the macro prior to converting the design file into configuration data. The macro manager provides the configuration data to the end user. Because only the macro manager has access to the macro, the possibility of unlicensed use of the macro is diminished.

Methods to securely configure an FPGA using macro markers

The present invention allows one portion of an FPGA to reconfigure another portion of the same FPGA. The invention makes use of input/output ports that can be connected on the input side to a frame register for loading configuration data into the FPGA. When a portion of the FPGA is to be reconfigured, data are loaded by a portion of the FPGA not being reconfigured into the frame register of the FPGA and addressed to the portion of the FPGA being reconfigured. Loading of the data is accomplished by forming a configuration data stream in the portion of the FPGA not being reconfigured, then applying the configuration data stream to an output buffer of the FPGA and forwarding that data to an input buffer that is connected to a frame register of the FPGA configuration structure.

FPGA system with user-programmable configuration ports and method for reconfiguring the FPGA

A table-based computer user interface and a method of providing design parameters are provided for configuring circuits for programmable ICs. A design database describing a circuit is displayed in table-based format on a computer screen display. The design database may include a memory map including data to be placed in bit-storage space in the target programmable IC. This design database requires no schematics or HDL description of the circuit, even for application-specific circuits and other complicated circuits. The desired parameters are entered by the user, typically using toggle buttons, pull-down menus, or keyboard entry. The selected parameters and memory map data are then entered into the design database, thereby configuring the design database in accordance with the selected parameters. In one embodiment, the user interface can also be used to display read data from a previously programmed programmable IC.

Memory map computer control system for programmable ICS

A programmable logic device (PLD) includes a plurality of logic resources, a plurality of multi-bit configuration memories (MBCMs), and a trigger logic structure. The plurality of MBCMs include multiple memory slices that allow the PLD to switch rapidly between configurations, or contexts. In one embodiment, at least one memory slice configures the PLD into a logic analysis context for providing on-chip testing. In one embodiment, the plurality of logic resources include a plurality of storage elements. State data generated by a user-defined context is stored in the plurality of storage elements. When the trigger logic structure provides a trigger signal, the PLD is reconfigured into the logic analysis context. The logic analysis context reads and processes the state data stored in the plurality of storage elements to test the performance of the user-defined context. In one embodiment, the storage elements are multi-bit micro-registers that store state data generated by a plurality of contexts implemented in the multiple-context PLD.

On-chip logic analysis and method for using the same

An FPGA includes an embedded non-volatile memory coupled to a configuration access port. The configuration access port allows the non-volatile memory to program the configuration memory of the FPGA. On power-on or reset, the non-volatile memory configures a first portion of the FPGA using configuration data stored in the non-volatile memory. Other portions of the FPGA can also be configured using the embedded non-volatile memory. Alternatively, an external configuration device can configure the other portions of the FPGA through a configuration port. Further, either the embedded non-volatile memory or the external configuration device can reconfigure the first portion of the FPGA.

Configuring an FPGA using embedded memory

The invention provides a structure and method for configuring an FPGA from a PROM using a boundary scan chain. A PROM is provided that comprises JTAG circuitry. Configuration data is stored in the PROM memory as in known PROMs. When the data is retrieved from the PROM memory it is provided on a standard JTAG Test Access Port (TAP). The JTAG-compatible PROM is included as part of a JTAG scan chain, preferably directly preceding the FPGA to be configured by the PROM. The PROM can be controlled either externally or via JTAG commands received down the scan chain. Therefore, a reconfiguration of the FPGA can be initiated via standard JTAG commands. In one embodiment, the PROM itself is programmed with the FPGA configuration data using the JTAG TAP port.

PROM with built-in JTAG capability for configuring FPGAs

A method is provided for configuring an FPGA using a decoder implemented in the FPGA. Specifically, an external configuration device or an embedded non-volatile memory configures a first portion of the FPGA as a decoder. Encoded configuration data is transferred to the decoder, which then configures other portions of the FPGA. In one embodiment, the decoder is a decompression unit, which decompresses compressed configuration data. In another embodiment, the decoder is an interpreter, which interprets configuration commands. In some embodiments, the portion of the FPGA used for the decoder can be reconfigured after the configuration of the other portions of the FPGA.

Decoder structure and method for FPGA configuration

The invention provides to the user a way of ascertaining the estimated delay through a circuit, by placing a timing attribute on the schematic symbol for the circuit that automatically displays the estimated delay. Reported delays may include maximum delay, typical delay, and/or minimum delay on the critical path. In a first embodiment, the schematic entry software consults a macro speeds file to obtain delay information for the macro. In a second embodiment, the macro delay information is added to the standard device speeds file. In a third embodiment, the symbol file (or other file) for the macro includes a formula for the critical path delay through the macro, based on the delays in the standard device speeds file. The schematic entry software therefore uses the standard device speeds file to calculate the macro delay. According to a second aspect of the invention, schematic-entry software accepts pointer-driven (e.g., mouse-driven) input designating starting and ending points on a path, and reports the path delay between these points. According to a third aspect of the invention, schematic-entry software accepts pointer-driven input designating a group of schematic symbols and reports the path delay on the critical paths through the circuit comprising the designated symbols.

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San Jose, CA, United States of America

Gary R Lawman