Fairchild Semiconductor Corporation

Fairchild Camera and Instrument Corp.

Gary R Burke

Tich T Dao

A microprocessor integrator circuit includes split nanocode memories which enables simultaneous execution of an arithmetic operation and an operand fetch for maximizing through-put. The circuit also includes a shared sequencing arithmetic logic unit which handles all microcode sequencing plus memory address sequencing. The circuit also provides nanocode sequencing which enables storage of constants and data in a microcode space which can include an off-chip writable control store. In addition, two level microcode is utilized to enable long routines to be vertically encoded without the overhead of a large number of read only memory outputs.

Floating point microprocessor with directable two level microinstructions

In a microprocessor having independent address and data paths and other pipeline architecture features, a control unit utilizes a PLA which stores microcoded instruction sequences. These sequences permit an operator at a console to read data from and write data to all the internal registers, any external memory location or the program counter. In addition, the PLA contains microcode which enables programs in external memory to be loaded from any location in memory and run by command from the console as well as to enable the operator to halt user program execution, read the pertinent internal registers, and then continue program execution such that single step execution for debug purposes is possible. The PLA also contains self-test microcode which permits the console operator to start a self-test sequence of instructions issued from the PLA which will test the functionality of the majority of the registers, multiplexers, and data paths in the machine as well as test the majority of the arithmetic and logical functions which can be carried out by arithmetic and logic unit of the microprocessor. The control unit also contains logic to support an external bus arbiter for use of the computer in a multiprocessor network with a common bus.

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Cupertino, CA, United States of America

Gary R Burke