Cypress Semiconductor Corporation

Ramtron International Corporation

Longitude Flash Memory Solutions Ltd.

Cypress Semiconductor Corporaation

Longitude Elash Memory Solutions Ltd

Gary Peter Moscaluk

Vijay Raghavan

Iulian Constantin Gradinariu

Roger J Bettman

Cristinel Zonte

Samuel Leshner

Vineet Argrawal

Bogdan I Georgescu

John W Tiede

Ryan Tasuo Hirose

Leonard Vasile Gitlan

John Eric Gross

Ashish Ashok Amonkar

Timothy John Williams

Harold Kutz

Igor G Kouznetsov

John J Silver

Systems and methods for driving a non-volatile memory device in a standby operating condition are disclosed. A standby detection circuit detects whether the non-volatile memory system is in a standby condition. In response to determining that the non-volatile memory system is in a standby condition, a bias control circuit provides bias currents to drivers of the non-volatile memory system in a standby mode.

Low standby power with fast turn on method for non-volatile memory devices

A method for driving a non-volatile memory system is disclosed. A standby detection circuit detects whether the nonvolatile memory system is in a standby condition. In response to determining that the non-volatile memory system is in a standby condition, a bias control circuit reduces bias currents provided to drivers of the non-volatile memory system in a standby mode. The non-volatile memory system is operated in the standby mode after the bias currents have been reduced, where an output signal indicating the standby mode is maintained until a read instruction is detected.

A method of erasing, during an erase operation, a non-volatile memory (NVM) cell of a memory device is disclosed. The erasing includes applying a first HV signal (VPOS) to a common source line (CSL). The CSL is shared among NVM cells of a sector of NVM cells. The first HV signal is above a highest voltage of a power supply. The erasing also includes applying the first HV signal to a local bit line (BL).

High voltage architecture for non-volatile memory

Low standby power with fast turn on for non-volatile memory devices

Circuits, systems, and methods for starting up analog devices are provided. One circuit includes an output node at an output voltage (VOUT), a comparator configured to be coupled to a reference voltage (VREF), a feedback loop coupling the output node to the comparator, and a turbo circuit coupled between the output and the output node. The turbo circuit is configured to increase VOUT, the comparator is configured to compare VOUT and VREF, and the turbo circuit is enabled and disabled based on the comparison of VOUT and VREF. One system includes an analog device coupled to the above circuit. A method includes enabling the startup portion to start up the driver portion when VOUT is outside a predetermined voltage of VREF, disabling the startup portion when VOUT is within the predetermined voltage, and enabling the driver portion to drive the analog device subsequent to disabling the startup portion.

Systems and methods for starting up analog circuits

A biasing circuit includes cascoded transistors including a first transistor and a second transistor. A first gate of the first transistor is coupled to a second gate of the second transistor at a first node. The circuit also includes a voltage control circuit coupled to at least one of the first transistor or the second transistor. The voltage control circuit is configured to change a voltage level of at least one of the first transistor or the second transistor to allow voltage domain transition of an output signal in view of a change in state of an input signal without ramping a supply signal of the biasing circuit.

Negative high voltage hot switching circuit

Apparatus, systems, and methods for providing high voltage to memory devices are provided. One apparatus includes a low voltage input and a two-rail level shifting. The two-rail level shifting is configured to increase the low voltage or to decrease the low voltage to an amount that is less than or equal to a ground potential based on the amount of the low voltage. A system includes a low voltage input for receiving a voltage and a two-rail level shifting coupled to the low voltage input. The two-rail level shifting is configured to increase the voltage to a positive voltage if the voltage is equal to a ground potential and decrease the voltage to a negative voltage if the voltage is greater than the ground potential. One method includes receiving a voltage, modifying the voltage to generate one of a plurality of output voltages, and providing the output voltage to a memory device.

Systems and methods for providing high voltage to memory devices

Circuits, systems, and methods for discharging loads are provided. One circuit includes a node coupled to a voltage source, a capacitor, a source-follower device coupled between the node and the capacitor, and a current source coupled to the capacitor. The source-follower device is configured to switchably couple the capacitor to the node to discharge the voltage source and the current source is configured to discharge the capacitor. One system includes the above circuit coupled to a memory device such that the circuit is configured to discharge voltage from the memory device. A method includes discharging, via a capacitor coupled to the memory device, a high voltage from the memory device and discharging, via a current source coupled to the capacitor, the high voltage from the capacitor. The capacitor is configured to discharge the high voltage within a predetermined range of time.

Systems and methods for discharging load capacitance circuits

A system includes power saving circuitry to revive a system controller from a sleep mode for performance of operations in an active mode. The system also includes a regulator including a floating gate reference device to generate output voltage and current capable of powering the power saving circuitry during the sleep mode. A method includes generating a reference voltage and current with a float gate device, and powering wake-up circuitry with the reference voltage and current while in a power saving mode. The wake-up circuitry is configured to activate a main system controller from the power saving mode.

Floating gate reference for sleep/hibernate regulator

A charge pump circuit has at least three stages: a pre-stage, a common stage and post stage. Each stage has three devices which are common. An NMOS device, which is called the charge injection device (CID), is controlled by a PMOS device during charge injection and an NMOS device during charge trapping. Also, each of the stages includes comparison stages for the CID in order to minimize the bulk to source voltage (Vbs) or bulk to drain voltage (Vbd). This greatly improves efficiency during the charge injection phase. Furthermore, the post-stage includes a comparison stage for the PMOS device since the threshold voltage increases as you increase the number of stages with the bulk tied to VPWR. The PMOS comparison stage should be inserted at the stage where the PMOS device begins to operate in the sub-threshold region, which is technology and voltage dependent.

Charge pump

Disclosed is a process, voltage and temperature compensated polarity conversion circuit comprising an input signal generator comprising an input signal having a first polarity, a variable frequency generator, a plurality of high voltage differential switches coupled to the variable frequency generator and a controllable threshold transmission gate circuit coupled to the input signal generator, coupled to the variable frequency generator and coupled to the plurality of high voltage differential switches. A method of polarity conversion and other embodiments are also disclosed.

Growing community of inventors

Colorado Springs, CO, United States of America

Gary Peter Moscaluk