International Business Machines Corporation

Lsi Logic Corporation

Lsi Corporation

Brocade Communications Systems, Inc.

Gary Paul McClannahan

Jonathan W Byrn

Gary Scott Delp

Chad Balling McBride

Robert Neal Carlton Broberg, Iii

George Wayne Nation

Mark William Branstad

John Emery Nordman

John Handley Shaffer

Todd Edwin Leonard

Albert Alfonse Slane

Michael K Eneboe

Philip Lynn Leichty

Kevin Gerard Plotz

Paul Gary Reuland

Matthew Scott Wingren

Thomas Sandoval

Robert N Broberg, Iii

Ronald Nick Kalla

Michael Raymond Trombley

Michael Joseph Carnevale

Gary Michael Lippert

Venkatesh Nagapudi

Todd Jason Youngman

Daniel Paul Wetzel

Yash V Bansal

Scott Thomas Senst

Gustavo Lau

A converged network adapter in sleep mode can allow a management entity to access and alter configuration of the network adapter over the network. Configuration data such as configuration parameters, firmware, and other data related to the network adapter can be stored in a memory, which can be coupled to a portion of the adapter that receives power during sleep mode. The management entity can send configuration messages to the adapter, which messages can include commands or instructions to read or write contents of the memory. The messages can include values of the configuration parameters to be altered, firmware code, etc. The management entity can also send configuration messages to a baseboard management controller (BMC) coupled to the adapter for message validation. The adapter and the BMC can send results of memory operations back to the management entity in response messages.

Systems and methods for reconfiguring a network adapter in sleep mode

A set of tools is provided herein that produces useful, proven, and correct integrated semiconductor chips. Having as input either a customer's requirements for a chip, or a design specification for a partially manufactured semiconductor chip, the tools generate the RTL for control plane interconnect; memory composition, test, and manufacture; embedded logic analysis, trace interconnection, and utilization of spare resources on the chip; I/O qualification, JTAG, boundary scan, and SSO analysis; testable clock generation, control, and distribution; interconnection of all of the shared logic in a testable manner from a transistor fabric and/or configurable blocks in the slice. The input customer requirements are first conditioned by RTL analysis tools to quickly implement its logic. The slice definition and the RTL shell provides the correct logic for a set of logic interfaces for the design specification to connect. The tools share a common database so that logical interactions do not require multiple entries. The designs are qualified, tested, and verified by other tools. The tools further optimize the placement and timing of the blocks on the chip with respect to each other and with respect to placement on a board. The suite may be run as batch processes or can be driven interactively through a common graphical user interface. The tools also have an iterative mode and a global mode. In the iterative mode, one or more of the selected tools can generate the blocks or modify a design incrementally and then look at the consequences of the addition, or change. In the global mode, the semiconductor product is designed all at once in a batch process as above and then optimized altogether. This suite of generation tools generates design views including a qualified netlist for a foundry to manufacture.

Suite of tools to design integrated circuits

A delay line calibration circuit and method are provided in which a programmable master delay line drives a delay clock and has a propagation delay that is a function of a delay setting. A delay counter is clocked by the delay clock and has a delay count. A reference counter is clocked by a reference clock and has a reference count. A control circuit controls the delay and reference counters, compares a representation of the delay count to a representation of the reference count and responsively generates a modified value for the delay setting to reduce a difference between the representations of delay count and the reference count.

Method and apparatus for calibrating a delay line

A method and apparatus for a cache line cut through reduces the latency and memory bandwidth of a data processing system. By cutting through or forwarding a cache line to the next processing element, data that has been read from a local memory into a local cache and altered by a processing element need not be restored to the local memory before it is sent to its destination target processing element. By eliminating the write back to the local memory for direct write through to the destination, performance is increased because the bandwidth and latency are decreased. In a preferred embodiment, the processing elements may be contained within a network processor and the altered data may be a header in one network protocol which needs to be modified to another protocol before transfer of the data along the network. Transfer of the data may be to another network processor, another processing element, or to another memory.

Cache line cut through of limited life data in a data processing system

Simplified process to design integrated circuits

A reconfigurable memory controller includes a plurality of communicatively coupled memory controllers. The plurality of memory controllers may be configured into a first configuration based on a grouping of memory controllers and then reconfigured into a second configuration based on a different grouping of memory controllers, where the first and second configurations have different performance bandwidths for accessing memory.

Reconfigurable memory controller

A method and apparatus are provided for implementing communications in a communications network. The apparatus for implementing communications includes a system interface to the communications network. A scheduler schedules enqueued cells and enqueued frames to be transmitted. A segmenter segments frames and cells in into cells or frames applied to a media adaptation block for transmission in a selected one of multiple modes.

Communications adapter for implementing communications in a network and providing multiple modes of communications

A method of handling an interrupt request in a computer system by programmably setting an override address associated with a specific interrupt service routine, and servicing an interrupt request based on the override address, which is different from a power-on default address associated with the same interrupt service routine. The method may determine whether the interrupt service routine is critical and, if so, set the override address to a physical location in the on-chip memory of the processing unit, instead of in the off-chip memory (RAM). Override address registers are accessed via the special purpose registers of the processing unit. A validation bit may be turned on in response to the setting of the override address, with both the default address and the override address being provided as separate inputs to a multiplexing device controlled by the validation bit. The override address is forwarded from the multiplexing device to an instruction fetch unit whenever the validation bit has been set. The result is decreased latency associated with interrupt handling, and increased flexibility in user definition of critical versus non-critical interrupts.

Exceptions and interrupts with dynamic priority and vector routing

Method, system and signal bearing medium for configuring an integrated circuit are provided. One embodiment provides a method for configuring an integrated circuit, comprising: providing a user interface for displaying one or more abstract data elements for user selection, wherein the one or more abstract data elements represent one or more controls associated with characteristics of the integrated circuit; receiving a user selection of an abstract data element; validating associated abstract rules for the user selected abstract data element; and validating product rules for the one or more product data elements associated with the user selected abstract data element, wherein the one or more product data elements represent one or more controllable features of the integrated circuit.

Reusable configuration tool

A method and Gigabit Ethernet communications adapter are provided for implementing communications in a communications network. A transmission queue is defined of data to be transmitted. A transmission rate is set for the transmission queue. Data to be transmitted are enqueued on the transmission queue. The transmission queue can be subdivided into multiple priority queues, for example, using time wheels, and a transmission rate is set for each transmission queue.

Communications methods and gigabit ethernet communications adapter providing quality of service and receiver connection speed differentiation

A memory controller circuit arrangement and method utilize a tuning circuit that dynamically controls the timing of memory control operations, rather than simply relying on fixed timing parameters that are either hardwired or initialized upon startup of a memory controller. Dynamic control over the timing of memory control operations typically incorporates memory test control logic that verifies whether or not a memory storage device will reliably operate using the dynamically-selected values of given timing parameters. Then, based upon the results of such testing, such dynamically-selected values are selectively updated and retested until optimum values are found. The dynamically-selected values may be used to set one or more programmable registers, each of which may in turn be used to control the operation of a programmable delay counter that enables a state transition in a state machine logic circuit to initiate performance of a memory control operation by the logic circuit. Dynamic tuning may also utilize a unique binary search engine circuit arrangement that updates one of two registers with an average of the current values stored in such registers based upon the result of a test performed using that average value. By selectively updating such registers, a fast convergence to an optimum value occurs with minimal circuitry.

Dynamically-tunable memory controller

A method and apparatus are provided for implementing direct memory access (DMA) with dataflow blocking for users for processing data communications in a communications system. A DMA starting address register receives an initial DMA starting address and a DMA length register receives an initial DMA length. A DMA state machine receives a control input for starting the DMA. The DMA state machine updates the DMA starting address to provide a current DMA starting address. The DMA state machine loads a DMA ending address. A DMA blocking logic receives the current DMA starting address and the DMA ending address and blocks received memory requests only within a current active DMA region.

Method and apparatus for direct memory access (DMA) with dataflow blocking for users

A memory controller circuit arrangement and method utilize a tuning circuit that controls the timing of memory control operations via one or more programmable delay counters. Each counter is programmed to cycle a selected number of clock cycles to delay performance of a memory control operation to meet a predetermined timing parameter for a memory storage device coupled to the controller. Through the use of programmable delay counters, a variety of memory storage devices having varying timing parameters may be supported by the same memory controller design. Moreover, the use of programmable delay counters permit a single path of execution in a memory controller state machine to support any number of timing parameter variations for a particular timing characteristic, as well as multiple timing characteristics.

Memory controller with programmable delay counter for tuning performance based on timing parameter of controlled memory storage device

A method and apparatus are provided for target addressing and translation in a non-uniform memory environment with user defined target tags. The apparatus for target addressing and translation includes a processor and a first address translation unit coupled to the processor. The first address translation unit translates an effective address (EA) to a real address (RA). The first address translation unit includes a target tag associated with each address translation. A second address translation unit translates a real address (RA) to a target address (TA). The second address translation unit includes a target tag associated with each address translation. A cache includes a cache directory and a target tag is stored into the cache directory with each cache fill.

Growing community of inventors

Rochester, MN, United States of America

Gary Paul McClannahan