Lattice Semiconductor Corporation

Gary P Powell

Phillip Johnson

William B Andrews

Harold Scholz

Fulong Zhang

A clock generator has a reset circuit and (at least) two dividers, where each divider divides a reference clock signal by a divisor value to generate an output clock signal. The reset circuit generates reset signals for the dividers, where the reset signals are delayed relative to one another by a selected number of reference clock cycles, such that the dividers generate output clock signals having a desired phase offset between them.

Output clock phase-alignment circuit

A set of interconnected delay stages, such as a voltage-controlled oscillator, has switch-controlled load circuitry connected to each output of each delay stage in the oscillator ring. In one embodiment, for each delay stage output, the switch-controlled load circuitry includes a switch, a transistor, and a current source. The switch is connected between the corresponding delay stage output and the transistor gate, the current source is connected between a power supply and the transistor drain, and the transistor source is connected to ground. In such a configuration, the transistor's gate-to-source capacitance can be applied to the corresponding delay stage output by closing the switch, for example, for lower-frequency operations. In addition, the output impedance of the current source decouples the capacitive load from the power supply, thereby substantially shielding the oscillator ring from noise in the power supply.

Noise-shielding, switch-controlled load circuitry for oscillators and the like

Clock generation techniques are disclosed to provide clock generation with duty cycle replication. The clock generation techniques may further compensate for clock insertion delays and minimize distortion due to clock distribution networks.

Clock generation

An apparatus and method for programmable lock detection and correction (PLDC) to a programmable accuracy in a digital delay-locked loop (DLL) based multiphase clock generator (MCG) is based on a DLL that utilizes a digital count to control the delay of a digitally controlled, multiple-tap delay line in its feedback path where stability of the digital count is used to qualify the determination of lock to a programmable accuracy and lock determination is based on combinatorial evaluation of the multiple phase outputs for the proper waveform relationships. The incidence of false lock corresponding to excessive delay through the delay line is addressed by a LOOPRESET signal that results in a reset of the digital count that controls the delay through the delay line. Additionally, programmability of the stability interval, the digital counter step size, and the accuracy of the lock provide control over lock acquisition time.

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Upper Macungie, PA, United States of America

Gary P Powell