Lucent Technologies Inc.

At+t Corp.

Gary P Powell

Richard G Stuby, Jr

Ho Trong Nguyen

William B Andrews

Satwant Singh

Barry K Britton

Kai-Kit Ngai

Zeljko Zilic

Carolyn W Spivak

Ronald T Modo

Hollis G Robertson

William H Smith Iii

The invention provides an input/output (I/O) signaling voltage range discriminator (and corresponding method) which is used to control a configurable logic device such as a configurable I/O buffer in a second electronic circuit in response to a detected signaling voltage range of a first electronic circuit. The discriminator outputs an indication of the signaling voltage range of the first electronic circuit to a configurable I/O buffer enabling it to adapt to the signaling levels used by the first electronic circuit. The I/O buffer, based on the indication provided by the discriminator, can then configure its logic to become tolerant and/or compatible with digital signals transferred to and from the first electronic circuit.

Signaling voltage range discriminator

The present invention provides an integrated circuit having an operating voltage adaptable buffer, capable of operating in different voltage signaling environments, which includes a control circuit that provides a clamping function to the signaling path under prescribed operating conditions and which also reliably biases the p-type transistor substrate voltage of the buffer to the most positive voltage seen by the buffer under all operating conditions occurring on the signaling path, thereby protecting the p-type transistors.

Operating voltage adapting buffer

The FPGA has an array of programmable logic cells (PLCs) surrounded by a ring of programmable input/output cells (PICs). In one embodiment, the pads of each pair of adjacent PICs, as well as internal routing resources of each of the two PICs, are programmably connected to a single global-signal spine, and the spine is programmably connected directly to only half of the perpendicular branches. Each of the branches can then connect to the cells in two adjacent rows/columns of the array to provide a global signal to any of the cells in the array while only using a branch per every two rows/columns of the device. The reduced number of spine-to-branch connections reduces the capacitive loading on the spines, thereby increasing the speed at which global signals can be transmitted. In addition, sharing spines between adjacent PICs reduces the number of spines in the FPGA by half, thereby providing additional layout space for other resources. Sharing branches also has the same effect as sharing spines in that the number of branches is reduced by half, also increasing global signal speed. These advantages are achieved without reducing the programming flexibility of the FPGA.

Global signal distribution with reduced routing tracks in an FPGA

An integrated circuit for providing a pin-for-pin replacement of a field programmable gate array (FPGA). The integrated circuit includes an emulation circuit for mimicking the programmable stage (e.g., initialization, configuration and start-up states) of the FPGA. The integrated circuit is designed to be transparent to the user/customer, thereby eliminating the need for a costly redesign of a user's circuit board.

Configuration pin emulation circuit for a field programmable gate array

A method and system, in which the relative physical placement of configurable logic blocks, signal routing networks, and clock distribution trees of the FPGA implementation is preserved on the mask programmable logic cell (MPLC) substrate after the conversion process is completed. By constraining the physical placement of corresponding structures on the MPLC substrate at the network level of the MPLC implementation, the relative signal and clock delays presented during the FPGA implementation are substantially maintained in the MPLC implementation, thereby assuring functional equivalence between the FPGA and MPLC implementations.

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Allentown, PA, United States of America

Gary P Powell