Intel Corporation

Institute for the Development of Emerging Architectures, L.l.c.

Other

Institute for the Development of Emerging Architecture L.l.c.

Hewlett-packard Company

Gary N Hammond

Koichi Yamada

Stephen G Burger

William R Bryg

Donald B Alpert

Nazar A Zaidi

Jonathan Kent Ross

James O Hays

Kevin C Kahn

Harshvardhan P Sharangpani

Judge K Arora

Kin-Yip Liu

Harsh Sharangpani

Kenneth D Shoemaker

Ken Shoemaker

Sunil Saxena

Jeffery J Baxter

Rajiv Gupta

Dale Calvin Morris

John H Crawford

Nhon Toai Quach

Michael L Ziegler

Jerome C Huck

Amy L Santoni

Hans J Mulder

Carl C Scafidi

John M Kessenich

Anand B Pai

Millind Mittal

Tse-Yu Yeh

Achmed Rumi Zahir

Ralph Michael Kling

Asit K Mallick

Gregory Scott Mathews

Kushagra V Vaid

Carol Linda Thompson

Yan Li

Mani Ayyar

Jack D Mills

Mustafiz R Choudhury

Jeff J Baxter

Stefan M Freudenberger

Ken Arora

Rohit Seth

Krishna M Yellamilli

William R Greene

Martin J Whittaker

Jim Hays

Hin L Leung

Felix Leung

Ganesh Subramaniyam

Pradeep Dubey

Russ Wunderlich

A tank or bed has a plurality of sidewalls that create a bed cavity and a Fresnel panel frame that includes at least one Fresnel panel. The Fresnel panel frame may be adjacent to the bed cavity and may cover at least a portion of the bed cavity. An amount of sludge may be contained within the bed cavity. When placed in sunlight, the heat enhanced by the Fresnel panels may heat the sludge sufficiently for the sludge to be used as fertilizer.

Wastewater sludge treatment device

A method of treating sludge using solar energy is provided. The present invention utilizes a Fresnel panel frame that includes at least one Fresnel panel. The Fresnel panel may cover at least a portion of a bed cavity. An amount of waste may be placed within the bed cavity. When placed in sunlight, the heat enhanced by the Fresnel panels may heat the waste sufficiently for safe easy disposal, recycling, or for the creation of fertilizer.

Method of treating sludge using solar energy

Embodiments of apparatuses and methods for improving performance in a virtualization architecture are disclosed. In one embodiment, an apparatus includes a processor and a processor abstraction layer. The processor abstraction layer includes instructions that, when executed by the processor, support techniques to improve the performance of the apparatus in a virtualization architecture.

Performance in a virtualization architecture with a processor abstraction layer

Embodiments include a system for minimizing storage space required for tracking load instructions through a pipeline in a processor. Store instructions are tracked in a separate queue and only load instructions that require speculation on data or addresses are tracked in a load table and flagged in the reorder buffer. This system improves system performance by reducing energy and space requirements.

Utilizing an advanced load address table for memory disambiguation in an out of order processor

A method and apparatus for providing a source operand for an instruction to be executed in a processor. Some embodiments may include a register file unit that has registers and a scheduler to schedule instructions. In some embodiments, the scheduler is to asynchronously receive an instruction and a source operand for that instruction, the source operand being received from the register file unit.

Method and apparatus to provide a source operand for an instruction in a processor

Embodiments include various methods, apparatuses, and systems in which a processor includes an out of order issue engine and an in-order execution pipeline. For some embodiments, the issue engine may be remote from the execution pipeline and execution resources may be many clock cycles away from the issue engine. The issue engine categorizes operations as at least one of either a speculative operations which perform computations, or an architectural operations which has potential to fault or cause an exception. Potentially excepting operations may be decomposed into two separate micro-operations: a speculative micro-operation, which is used to generate data results speculatively so that operations dependent on the results may be speculatively issued, and an architectural micro-operation, which signals the faulting condition for the excepting operation. A STORE operation becomes an architectural operation and all previous faulting conditions may be guaranteed to have evaluated before a STORE is issued.

Decomposing architectural operation into speculative and architectural micro-operations for speculative execution of others and for violation check

A method for managing virtual memory addresses includes associating a guest identifier (ID) with a virtual machine accessing a virtual memory address. A physical memory address is retrieved corresponding to the virtual memory address utilizing the guest ID. Other embodiments are described and claimed.

Method and apparatus for managing virtual addresses

Embodiments include various methods, apparatuses, and systems in which a processor includes an out of order issue engine and an in-order execution pipeline. For some embodiments, the issue engine may be remote from the execution pipeline and execution resources may be many clock cycles away from the issue engine. The issue engine categorizes operations as at least one of either a speculative operations, which perform computations, or an architectural operation, which has potential to fault or cause an exception. Potentially excepting operations may be decomposed into two separate micro-operations: a speculative micro-operation, which is used to generate data results speculatively so that operations dependent on the results may be speculatively issued, and an architectural micro-operation, which signals the faulting condition for the excepting operation. A STORE operation becomes an architectural operation and all previous faulting conditions may be guaranteed to have evaluated before a STORE is issued.

Resolving all previous potentially excepting architectural operations before issuing store architectural operation

According to one embodiment, a method is disclosed. The method includes determining whether the temperature of a central processing unit (CPU) exceeds a predetermined threshold. In addition, the method includes generating a first interrupt if the temperature of the CPU exceeds the predetermined threshold and transitioning from a first execution mode to a second execution mode.

Method and apparatus for lowering the die temperature of a microprocessor and maintaining the temperature below the die burn out

Embodiments include various methods, apparatuses, and systems in which a processor includes an out of order issue engine and an in-order execution pipeline. For some embodiments, the issue engine may be remote from the execution pipeline and execution resources may be many clock cycles away from the issue engine The issue engine categorizes operations as at least one of either a speculative operation, which perform computations, or an architectural operation, which has potential to fault or cause an exception. Potentially excepting operations may be decomposed into two separate micro-operations: a speculative micro-operation, which is used to generate data results speculatively so that operations dependent on the results may be speculatively issued, and an architectural micro-operation, which signals the faulting condition for the excepting operation. A STORE operation becomes an architectural operation and all previous faulting conditions may be guaranteed to have evaluated before a STORE is issued.

Ordering scheme with architectural operation decomposed into result producing speculative micro-operation and exception producing architectural micro-operation

The present invention provides a computer system that is capable of operating in a first or second cache coherency mode according to the operating environment in which the computer system is booted to run. If the operating environment supports memory attribute aliasing (MAA), the computer system implements a cache coherency mechanism that supports MAA. If the operating environment does not support MAA, the computer system implements a cache coherency mechanism that does not support MAA.

Flexible mechanism for enforcing coherency among caching structures

Fast exception processing is disclosed. In one embodiment, a system includes a splice cache, an exception logic, and an instrumentation mechanism. The splice cache contains one or more lightweight handlers. The exception logic is coupled to the splice cache and determines whether the corresponding lightweight handler for an exception is located in the splice cache. The instrumentation mechanism is coupled to the splice cache. The instrumentation mechanism inserts the lightweight handler into an execution stream.

Fast exception processing

The present invention is a method and apparatus to map virtual memory space. A region register file provides a region identifier for a virtual address in the virtual memory space. The virtual address includes a virtual region number and a virtual page number. A virtual page table look-up circuit is coupled to the region register file to generate a page table entry (PTE) virtual address from virtual address parameters. The virtual address parameters include the virtual address.

Virtual memory mapping using region-based page tables

An article representing a processor providing event handling functionality is described. According to one embodiment of the invention, the article includes a machine readable medium storing data representing a processor including an instruction set unit and an event handling unit, as well as a first plurality of event handlers that includes a first event handler. The instruction set unit is to support a first and second instruction sets. Problems that arise during the processing of instructions from the first and second unit are to cause the article to execute the appropriate one of the first plurality of event handlers. At least some of the first set of events are mapped to different ones of the first plurality of event handlers. All of the second set of events are mapped to the first event handler.

Article for providing event handling functionality in a processor supporting different instruction sets

A computer system enters or exits a sleeping state, such as the ACPI &ldquo;S &rdquo; state, in response to a sleep or wake event. Upon detecting the sleep or wake event, a system component generates a sleep or wake signal that instructs the computer to enter or exit the sleeping state. This sleep or wake signal is of a type to which the computer's processor does not respond. Therefore, a PMI signal is asserted in response to the sleep or wake signal. The PMI signal, when asserted, causes the processor to halt program execution.

Placing a computer system into a sleeping state

Growing community of inventors

Campbell, CA, United States of America

Gary N Hammond