International Business Machines Corporation

Lsi Corporation

Lsi Logic Corporation

Avago Technologies General IP (Singapore) Pte. Ltd.

Gary Michael Lippert

Donald Lee Freerksen

George Wayne Nation

Judy M Gehman

John M Nystuen

Gary Scott Delp

Sheldon Bernard Levenstein

John David Irish

Jonathan W Byrn

Gary Paul McClannahan

Steven Mark Emerson

Srinivasa Rao Kothamasu

Farnaz Mounes-Toussi

Jerome M Meyer

Daniel Paul Wetzel

Donald Gabrielson

Scott E Greenfield

A cache controller configured to detect a wait type (i.e., a wait event) associated with an imprecise collision and/or contention event is disclosed. The cache controller is configured to operatively connect to a cache memory device, which is configured to store a plurality of cache lines. The cache controller is configured to detect a wait type due to an imprecise collision and/or collision event associated with a cache line. The cache controller is configured to cause transmission of a broadcast to one or more transaction sources (e.g., broadcast to the transaction sources internal to the cache controller) requesting the cache line indicating the transaction source can employ the cache line.

Cache system for managing various cache line conditions

An apparatus for handling anomalies in a hardware system including a master device and at least one slave device coupled with the master device through an interconnect device is provided. The apparatus includes at least one controller operative to receive status information relating to the slave device. The status information is indicative of whether an anomaly is present in the slave device and/or the interconnect device. The controller is operative to generate output response information as a function of the status information relating to the slave device for detecting and/or responding to hardware system anomalies in a manner which reduces a need for resetting the hardware system to return to normal operation.

Proxy responder for handling anomalies in a hardware system

An apparatus having a cache configured as N-way associative and a controller circuit is disclosed. The controller circuit may be configured to (i) detect one of a cache hit and a cache miss in response to each of a plurality of access requests to the cache, (ii) detect a collision among the access requests, (iii) queue at least two first requests of the access requests that establish a speculative collision, the speculative collision occurring where the first requests access a given congruence class in the cache and (iv) delay a line allocation to the cache caused by a cache miss of a given one of the first requests while the given congruence class has at least N outstanding line fills in progress.

Managing cache line allocations for multiple issue processors

A method for generalizing design attributes in a design capture environment comprising the steps of (A) defining a procedure for adding one or more auxiliary configurators to a tool or suite of tools, (B) linking the auxiliary configurators to predetermined object points in an abstracted design and (C) defining a procedure for the tool or suite of tools to reference the one or more auxiliary configurators, wherein the auxiliary configurators are neither referenced by a core nor built into the tool or suite of tools.

Method for generalizing design attributes in a design capture environment

A system for RTL test insertion in an integrated circuit layout pattern includes a core module, a test wrapper, and a smart wrapper. The core module describes a function defined by logical elements, interconnections between logical elements, input pins and output pins. The test wrapper is adapted to encapsulate the core module and to create test pins representing the core module. The smart wrapper is adapted to encapsulate the test wrapper and to assign the test pins to a non-asserted state. The smart wrapper is adapted to place an assertion on one or more of the test pins for static or dynamic testing of the integrated circuit layout pattern.

Method for abstraction of manufacturing test access and control ports to support automated RTL manufacturing test insertion flow for reusable modules

A delay line calibration circuit and method are provided in which a programmable master delay line drives a delay clock and has a propagation delay that is a function of a delay setting. A delay counter is clocked by the delay clock and has a delay count. A reference counter is clocked by a reference clock and has a reference count. A control circuit controls the delay and reference counters, compares a representation of the delay count to a representation of the reference count and responsively generates a modified value for the delay setting to reduce a difference between the representations of delay count and the reference count.

Method and apparatus for calibrating a delay line

A multi-processor system includes a system bus communicating between processors, and a bus arbiter. Responsive to a cache line invalidation command, a processor cache conditionally casts back the cache line to a transition cache. Based on the system response to the invalidation command, the transition cache either discards the cast back or writes it to main memory. The processor also converts an exclusive read command requiring a reservation to non-exclusive if the reservation has been lost before placing the command on the system bus. Furthermore, the transition cache may shift memory coherency image state for a non-exclusive command, which is waiting for data to return, if a command involving the same real address is snooped. Responsive to a cache line request, the cache copies that cache line to the transition cache and updates cache line state. The transition cache holds the cache line pending system response.

Method for increasing efficiency in a multi-processor system and multi-processor system with increased efficiency

The multi-processor system according to the present invention includes at least two processors, a system bus providing communication between the responses to commands on the system bus. One of the processors generates a snoop response to a command, associated with the same real address as the snooped command, which issued from the processor. In response to a command requesting invalidation of a cache line, a cache within the processor conditionally casts back the cache line to a transition cache in the processor. Based on the system response to the invalidation command, the transition cache either discards the cast back or converts the cast back into a command for writing the cache line in the main memory of the system. The processor also converts an exclusive read command requiring a reservation to a non-exclusive read command if that reservation has been lost prior to placing the command on the system bus. Furthermore, the transition cache in the processor may shift the memory coherency image state for a non-exclusive command, which is waiting for data to return, if a command associated with the same real address is snooped. In response to a command requesting a cache line, the cache in the processor copies that cache line to the transition cache and updates the state for the cache line. The transition cache holds the cache line until a system response is received.

According to the present invention, an apparatus and method for improving reads from and writes to shared memory locations is disclosed. By giving writes priority over reads, the current invention can decrease the time associated with certain sequences of reads from and writes to shared memory locations. In particular, load-invalidate-load sequences are changed to load&mdash;load sequences with the current invention. Furthermore, contention for a shared memory location will be reduced in particular situations when using the current invention.

Apparatus and method to improve performance of reads from and writes to shared memory locations

In a shared memory system, a plurality of requesters issue requests for particular memory addresses over a system bus. Requests, if denied, are later reissued after a controlled reissue delay. The reissue delay for a particular request is controllably varied in response to the number of requests being issued by requesters other than that which issued the request. Typically, the number of requests issued by other requesters for a common memory address as the particular request is tracked, and the reissue delay is controllably increased as the number of such requests increases. As such, the frequency that requests for highly contended memory addresses (which are more likely to be denied) is decreased relative to requests for less contended addresses, thereby freeing bandwidth on the system bus for requests that are more likely to be granted.

Controlled reissue delay of memory requests to reduce shared memory address contention

A data processing system, circuit arrangement, integrated circuit device, program product, and method improve system response by disregarding extraneous retry signals during the generation of a prioritized response signal from the response signals output from various snooper devices coupled to one another over a shared memory interface. In particular, it has been determined that a subset of retry signals issued by various snooper devices that snoop memory access requests do not have any a bearing upon the ultimate determination of whether or not a particular memory address, or cache line therefor, is stored in any of the snooper devices. As a result, by disregarding these extraneous retry signals, such access requests may be permitted to proceed without having to be reissued, thereby minimizing the time required to process such requests, and eliminating the extraneous traffic that would otherwise be present on the interface. Extraneous retry signals may be disregarded, for example, by prioritizing to a higher relative priority any response signal that indicates that information from a memory address, or cache line therefor, is stored in a single snooper device. As another example, response signals that indicate that the information from a requested memory address is stored in multiple snooper devices may also be prioritized relative to a retry signal if the request will not modify the information in the memory address.

Circuit arrangement and method of maintaining cache coherence utilizing snoop response collection logic that disregards extraneous retry responses

A memory cache system is used in a multiprocessor environment. The first processor accesses data using a first level,cache, and the second processor accesses data using a second level,cache. A storage control circuit is positioned between the first and second level,caches and a level,cache and main memory. The level,cache maintains copies of data in main storage and further maintains an indication of those level,caches having copies of data and whether those copies have been modified. When a processor accesses data that is not resident in the connected level,cache, a request is delivered to the level,cache for this data. The level,cache then determines whether it can return a copy of the data to the level,cache or must access the data from main memory. Also, when the level,cache determines that another level,cache is storing a modified copy of the data, the level,cache returns to the storage control circuit a pointer to the level,cache having the modified copy of the data; the storage control circuit then causes the level,cache having a modified copy of the data, to transfer the modified data to the requesting level,cache without returning the data to the level,cache or main memory. This ameliorates the effects of repeated writes to the same data by the multiple processors.

Peer-to-peer cache moves in a multiprocessor data processing system

The multi-processor system according to the present invention includes at least two processors, a system bus providing communication between the processors, and a bus arbiter generating system responses to commands on the system bus. One of the processors generates a snoop response to a snooped command based on the system response to a command, associated with the same real address as the snooped command, which issued from the processor. In response to a command requesting invalidation of a cache line, a cache within the processor conditionally casts back the cache line to a transition cache in the processor. Based on the system response to the invalidation command, the transition cache either discards the cast back or converts the cast back into a command for writing the cache line in the main memory of the system. The processor also converts an exclusive read command requiring a reservation to a non-exclusive read command if that reservation has been lost prior to placing the command on the system bus. Furthermore, the transition cache in the processor may shift the memory coherency image state for a non-exclusive command, which is waiting for data to return, if a command associated with the same real address is snooped. In response to a command requesting a cache line, the cache in the processor copies that cache line to the transition cache and updates the state for the cache line. The transition cache holds the cache line until a system response is received.

The processor includes at least a lower and a higher level non-inclusive cache, and a system bus controller. The system bus controller snoops commands on the system bus, and supplies the snooped commands to each level of cache. Additionally, the system bus controller receives the response to the snooped command from each level of cache, and generates a combined response thereto. When generating responses to the snooped command, each lower level cache supplies its responses to the next higher level cache. Higher level caches generate their responses to the snooped command based in part upon the response of the lower level caches. Also, high level caches determine whether or not the cache address, to which the real address of the snooped command maps, matches the cache address of at least one previous high level cache query. If a match is found by a high level cache, then the high level cache generates a retry response to the snooped command, which indicates that the snooped command should be resent at a later point in time, in order to prevent a collision between cache queries.

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Kasson, MN, United States of America

Gary Michael Lippert