Active-semi, Inc.

Apd Semiconductor, Inc.

Maxim Integrated Products, Inc.

Pakal Technologies, LLC

Gary Michael Hurtz

David J Kunst

Steven Huynh

Trey Roessig

Matthew Alan Grant

Vladimir Rodov

Geeng-Chuan Chern

Paul C Chang

Richard A Blanchard

Richard Landry Gray

Paul McKay Moore

Karl Richard Volk

Ching-Lang Chiang

Jianren Bao

Trinh Khac Hue

Andrew J Mrizek

Quang Khanh Dinh

A design technique is disclosed that divides up a cellular power switch into different size segments. Each segment is driven by a different driver circuit. The selection of the combination of segments is made to minimize the combined conduction and switching losses of the power switch. For example, for very light loads, switching losses dominate so only a small segment is activated for driving the load. For medium and high load currents, conduction losses become more significant, so additional segments are activated to minimize the total losses. In one embodiment, the number of cells in the segments is binary weighted, such as 1&#xd7;, 2&#xd7;, and 4&#xd7;, so that there are seven different combinations of segments. The drivers may be configured to achieve the same or different slew rates of the segments, such as to reduce transients. The segments may all be in the same die or a plurality of dies.

Insulated gate power device with independently controlled segments

A programmable analog tile integrated circuit is configured over a standardized bus by communicating tile configuration information from a first integrated circuit tile, through a second integrated circuit tile, to a third integrated circuit tile. Each of the three integrated circuit tiles is part of an integrated circuit. The standardized bus is formed when the tiles are placed adjacent one another. Data bus and control signal conductors of the adjacent tiles line up and interconnect such that each signal conductor is electrically connected to every tile. Tile configuration information may be written to a selected register identified by an address in any selected one of the tiles using the data bus and control lines, regardless of the relative physical locations of the tile sending and the tile receiving the information. Thus, tile configuration information may pass from one tile to another tile, through any number of intermediate tiles.

Communicating configuration information across a programmable analog tile to another tile

A programmable analog tile integrated circuit configuration tool communicates a power management control characteristic query soliciting control requirement information for a novel Power Management Integrated Circuit (PMIC) tile in a Multi-Tile Power Management Integrated Circuit (MTPMIC). The configuration tool receives a user response to the query indicating control requirements across a network. The PMIC tile includes configuration registers. Configuration information bit values stored in the configuration registers control the operational characteristics of the functional circuitry of the tile. The configuration registers of each novel PMIC tile are accessible at pre-defined addresses on a standardized bus of the MTPMIC. In response to the user response, the configuration tool generates appropriate tile configuration information for loading the configuration registers such that the PMIC tile within the MTPMIC is programmed to satisfy the user's control requirements.

Programmable analog tile configuration tool

A programmable analog tile integrated circuit placement tool allows a user to manipulate a graphical representation of a first power management integrated circuit (PMIC) tile with respect to a graphical representation of a second PMIC tile in a proposed Multi-Tile Power Management Integrated Circuit (MTPMIC). The novel PMIC tiles have pre-defined physical structures including a bus portion and a memory structure for storing configuration information for configuring the tile. When appropriately placed in a MTPMIC, the bus portions of the selected tiles automatically form a standardized bus that accommodates all signal communication required for a functioning MTPMIC. A remote user with minimal training in analog circuit design may command the placement of individual tiles in a proposed MTPMIC layout. Upon receiving a user response indicating satisfaction with the placement of PMIC tiles, the tool quickly and automatically generates physical layout data suitable for fabrication of the MTPMIC.

Programmable analog tile placement tool

An Analog Tile Selection, Placement, Configuration and Programming (ATSPCP) tool communicates a power management characteristic query over a network. The query is displayed to a user on a webpage. The query is a solicitation for desired characteristics of a Power Management Integrated Circuit (PMIC). After receiving user requirements in a response to the query, the tool selects a number of power management integrated circuit tiles having pre-defined physical structures. The pre-defined structure of each tile includes a bus portion and a memory structure for storing configuring information for the tile. When combined in a Multi-Tile Power Management Integrated Circuit (MTPMIC), the bus portions of the selected tiles automatically form a standardized bus that accommodates all signal communication required for a functioning MTPMIC that meets the user requirements. The ATSPCP tool combines the physical layout data of each selected PMIC tile to form composite physical layout data for the overall MTPMIC.

Analog tile selection, placement, configuration and programming tool

A single terminal is used to configure an integrated circuit into one of three states. A circuit within the integrated circuit is coupled to the terminal and determines whether the terminal: 1) is coupled by a low impedance to a voltage source, or 2) is coupled by a medium impedance to the voltage source, or 3) is floating or substantially floating. The circuit asserts a first digital logic signal when the circuit determines that the terminal is coupled by the low impedance to the voltage source. The circuit asserts a second digital logic signal when the circuit determines that the terminal is coupled by the medium impedance to the voltage source. The circuit asserts a third digital logic signal when the circuit determines that the terminal is floating or substantially floating. The terminal and circuit are particular suited for use in a Power Management Unit (PMU) Integrated Circuit.

Multi-function input terminal of integrated circuits

A method involves detecting an inrush current that flows out of a USB port of a first electronic device when a central processing unit (CPU) of the first electronic device is not being powered. The inrush current is detected by a novel inrush current detect circuit when a second electronic device is connected to the USB port. In one example, the first electronic device is a laptop computer having a battery and a USB DC-to-DC converter. The inrush current detect circuit enables the USB DC-to-DC converter such that the USB DC-to-DC converter receives power from the battery and supplies a regulated voltage to the second electronic device through the USB port while the CPU remains unpowered (not drawing power from the battery).

USB port with smart power management

A driver circuit (for example, in a switching power supply or in a Class-D switching amplifier) drives a gate of a switch during a transition with a low output impedance during an initial period and then for the remainder of the transition drives the gate with a midrange output impedance. The switch in turn switches current flow through an inductor. The driver circuit includes a 'Drive Node Voltage Dependent Impedance Circuit' (DNVDIC) that couples the gate to a supply voltage node. In one embodiment, there are two resistive current paths through the DNVDIC. A non-linear device in the first current path switches from having a small to a large impedance when a voltage drop across the device falls below a threshold voltage. The resulting increase in impedance of the first current path decreases voltage edge rates and reduces noise, whereas the low initial impedance reduces transition power losses.

Switch driver with low impedance initial drive and higher impedance final drive

A programmable analog tile integrated circuit programming tool communicates a power management control characteristic query soliciting control requirement information for a novel power management integrated circuit (PMIC) tile in a multi-tile power management integrated circuit (MTPMIC). The programming tool receives a user response to the query indicating control requirements across a network. The novel PMIC tiles have a pre-defined physical structure including all memory structures required for configuration of each tile and a bus portion. When combined in a multi-tile power management integrated circuit (MTPMIC), the bus portions of the selected tiles automatically form a standardized bus that accommodates all signal communication required for a functioning MTPMIC. The memory structure of each tile is individually addressable via the standardized bus. Thus, in response to control requirements, the programming tool programs a PMIC tile that is part of a MTPMIC to meet the control requirements.

Programmable analog tile programming tool

A single terminal is usable to configure an integrated circuit into one of three states. A circuit within the integrated circuit is coupled to the terminal and determines whether the terminal: 1) is tied low by an external connection, or 2) is tied high by an external connection, or 3) is floating or is substantially floating. If the circuit determines that the terminal is floating or is substantially floating, then the circuit sets an operational characteristic of a portion of the circuit (for example, sets a maximum current with which the circuit charges a battery) to have a value that is a function of a resistance of an external resistor coupled to the terminal. If no external resistor is present, then the terminal is floating and the operational characteristic is set to have a zero value. The terminal and circuit are particularly suited to use in a USB battery charger.

Multi-function input terminal

A power device having vertical current flow through a semiconductor body of one conductivity type from a top electrode to a bottom electrode includes at least one gate electrode overlying a gate insulator on a first surface of the body, a channel region of second conductivity type in the surface of the body underlying all of the gate electrode, a first doped region of the second conductivity type contiguous with the channel region and positioned deeper in the body than the channel region and under a peripheral region of the gate electrode, and a second doped source/drain region in the surface of the body abutting the channel region and adjacent to the gate electrode. When the gate is forward biased, an inversion region extends through the channel region and electrically connects the first electrode and the second electrode with a small Vnear to the area between adjacent P bodies being flooded with electrons and denuded of holes. Therefore, at any forward bias this area conducts as an N-type region. When the gate electrode is reverse biased, the long channel region underlying the full length of the gate electrode reduces reverse leakage current.

Power device having reduced reverse bias leakage current

Current source methods and apparatus for light emitting diodes providing constant diode current and illumination in the presence of voltage and process variations. The method comprises providing a predetermined current through a first transistor, and mirroring the current through the first transistor to at least one additional transistor while holding the voltage across the first transistor to a predetermined value, wherein each additional transistor is coupled in series with a light emitting diode. An exemplary circuit, as well as various illustrative applications are disclosed.

Current source methods and apparatus for light emitting diodes

A semiconductor current limiting device is provided by a two-terminal vertical N(P)-channel MOSFET device having the gate, body, and source terminals tied together as the anode and the drain terminal as the cathode. The doping profile of the body is so tailored with ion implantation that a depletion region pinches off to limit current. The body comprises a shallow implant to form a MOS channel and an additional deep implant through a spacer shielding the channel area. Implanted a higher energies and at an acute angle, the deep implant protrudes into the regular current path of the vertical MOSFET.

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Pleasanton, CA, United States of America

Gary Michael Hurtz