Advanced Micro Devices Corporation

Gary Michael Godfrey

Alfred C Hartmann

J Andrew Lambrecht

David James Borland

Lloyd W Gauthier

Richard G Russell

Daniel P Mann

David Francis Tobias

Mark Tracy Ellis

Donald G Craycraft

Jim Mergard

Floyd Goodrich, Iii

A computer chip having on-chip internetworked modules and implementing a network protocol for on-chip and, also preferably, off-chip data transfers. The modules on chip are interconnected through a plurality of on-chip packet-switched local area networks or LANs. The familiar Internet topology may be implemented on-chip with each module being treated as a &ldquo;host.&rdquo; A plurality of network interconnect (e.g. routers, gateways, etc.) may also be provided to interconnect the plurality of LANs. The computer chip implements a network protocol for on-chip data transfer. The network protocol may be TCP/IP. In that case, the computer chip itself may be treated as an Internet. This flexible chip architecture in that the computer chip may have modules clustered conveniently according to functionality, and the various modules may interact with one another without overburdening the chip packing density. An addressing scheme based on a modified TCP/IP protocol and involving an internetworked-chip module address (ICMA) is disclosed. Intermodule and internetwork data communication on the chip may be easily accomplished using internetworked-chip module addresses.

On-chip local area network

A system-on-a-chip with a variable bandwidth bus. The integrated circuit includes at least one bus, a clock, a plurality of modules coupled to the bus and operable to transfer and receive data on the bus, and a bus controller coupled to the bus that controls data transfers on the bus. The modules are operable to generate requests to the bus controller to perform transfers on the bus. Each request comprises an identifier which identifies one or more receiving modules, a transfer size value which specifies the amount of data to be transferred, and a timing value providing a time frame within which the requested data transfer should occur. Thee bus controller receives the requests, analyzes the timing value, and selectively allocates bandwidth on the bus based on the timing value, the bus controller may also examine the transfer size value or a priority value, and further determine a minimum rate of transfer required to provide the bandwidth on the bus to meet the time frame within which the requested transfer should occur. The integrated circuit may further comprises a power control device coupled to or part of the bus controller, which monitors power consumption and provides power conservation information to the bus controller. The bus controller may further adjust usage of the bus in response to the power conservation information provided by the power control device. The bus may be a time division, multiple access (TDMA) bus. The bus controller may enable data transfers on the TDMA bus only during assigned time slots of assigned frequency and assigned length. The bus controller may also further adjust assignment of the TDMA bus in response to the power conservation information.

System-on-a-chip with variable bandwidth

A system-on-a-chip with a variable clock rate bus. The integrated circuit includes at least one bus, a clock, a plurality of modules coupled to the bus and operable to transfer and receive data on the bus, and a bus controller coupled to the bus that controls data transfers on the bus. The modules are operable to generate requests to the bus controller to perform transfers on the bus. Each request comprises an identifier which identifies one or more receiving modules, a transfer size value which specifies the amount of data to be transferred, and a timing value providing a time frame within which the requested data transfer should occur. Thee bus controller receives the requests, analyzes the timing value, and selectively adjusts the clock rate of the bus based on the timing value. The bus controller may also examine the transfer size value or a priority value, and further determine a minimum rate of transfer required to provide the bandwidth on the bus to meet the time frame within which the requested transfer should occur. The integrated circuit may further comprises a power control device coupled to or part of the bus controller, which monitors power consumption and provides power conservation information to the bus controller. The bus controller may further adjust usage of the bus in response to the power conservation information provided by the power control device. The bus may be a time division, multiple access (TDMA) bus. The bus controller may enable data transfers on the TDMA bus only during assigned time slots of assigned frequency and assigned length. The bus controller may also further adjust assignment of the TDMA bus in response to the power conservation information.

System-on-a-chip with variable clock rate

A computing system employs an unicode driver to access and control peripheral devices by abstracting commands and status data to a level above register sets of similar but potentially incompatible peripheral devices. A unicode may be generated by an operating system or the unicode driver. Unicodes are routed by a device configuration interface that passes the unicodes between the unicode driver and peripheral devices. The peripheral devices include command decoders for performing conversion between unicodes and device-specific instructions. The use of unicode drivers eliminates duplicate driver code and simplifies device configuration for the computing system.

Unicode-based drivers, device configuration interface and methodology for configuring similar but potentially incompatible peripheral devices

The scalable virtual timer system or subsystem implements multiple hardware timers with minimal silicon overhead. In one embodiment, for each virtual timer of a plurality of virtual timers, a content addressable memory stores a sum of an &ldquo;initial state&rdquo; of a free running counter and a desired count duration for the virtual timer. When the stored value matches a current state of the free running counter, the content addressable memory generates a terminal count for the virtual timer. In an alternative embodiment, for each virtual timer, a period register of a set of period registers stores a sum of a desired count duration for a virtual timer and an &ldquo;initial state&rdquo; of the free running counter. A comparator of a set of comparators generates a terminal count for a virtual timer when a current state of the free running counter matches the sum stored in a period register associated with the virtual timer. A state of the free running counter may be read through software, such as by an execution unit, or through hardware, such as by an adder.

Scalable virtual timer architecture for efficiently implementing multiple hardware timers with minimal silicon overhead

A microcontroller has many miscellaneous logics. The miscellaneous logic can include input/outputs of combinational logic or peripheral devices of the microcontroller, storage devices such as latches, or registers. The miscellaneous logic is coupled to multiple stages of scan cells. The multiple stages can be used as a buffer while the last stage of scan cells are scanned out. A predetermined stage of scan cells are coupled together to form a scan path where data from the miscellaneous logic can be outputted to an external memory. In one embodiment, the predetermined stage is the last stage of scan cells. A trigger signal is used to shift the data from the miscellaneous logic to the next stage of scan cells. Once the last stage of scan cells are loaded, a clocking signal can be provided so that the data in the predetermined stage of scan cells is scanned out. The present invention provides among other things, a graceful way to capture data from miscellaneous logic of the microcontroller using scan hardware.

Transparently gathering a chips multiple internal states via scan path and a trigger

A system provides pseudo-concurrency for a volatile memory and a non-volatile memory on a same data bus. In one system embodiment, the volatile memory is coupled to its own address bus, and the non-volatile memory is coupled to its own address bus. In another system embodiment, the volatile memory and non-volatile memory are coupled to a multiplexed address bus. Concurrent with an access cycle to the volatile memory, the non-volatile memory may be precharged. After the access cycle to the volatile memory, a data cycle to a non-volatile memory may be executed. Concurrent with an access cycle to the non-volatile memory, the volatile memory may be precharged. After the access cycle to the non-volatile memory, a data cycle to the volatile memory may be executed.

Pseudo-concurrency between a volatile memory and a non-volatile memory on a same data bus

An on-chip programmable delay line is provided for controlling timing of an embedded system. A delay register is coupled to a processor. The delay register stores a delay or control value responsive to the processor. The on-chip programmable delay line is coupled to the delay register and delays a signal responsive to the delay value. The relationship between dynamic random access memory (DRAM) signals, such as row address strobe (RAS) and column address strobe (CAS), can thus be adjusted. In addition, the on-chip programmable delay line can be utilized with a device that includes an input that is not synchronous to a system clock.

Technique for controlling system bus timing with on-chip programmable delay lines

A computer chip including a data transfer network which comprises a plurality of communications links for transmitting data, a plurality of communication nodes, and a plurality of modules. Each of the communication nodes is directly connected to two or more other communication nodes through respective ones of the communications links. Each communication node is operable to communicate data over the respective one of the communications links. Each module is coupled to at least one of the communication nodes, and the modules are operable to communicate with each other through the communication nodes. The communication nodes are operable to create dynamic routes for the data transferred between any two or more of the plurality of modules over the respective ones of the communications links. The communication nodes form the dynamic routes controlled by a network configuration manager.

Scalable mesh architecture with reconfigurable paths for an on-chip data transfer network incorporating a network configuration manager

A debugging environment maintains object information (e.g., object size) concurrently with data optimization operations by a write buffer of a target system. Within the target system, a system bus is coupled between a system memory and a microcontroller. A data optimization operation by the write buffer is detected by monitoring of a merge signal of the system bus by a bus monitoring device. When a data optimization operation is detected, data optimization attributes (e.g., object information, data and address) associated with the data optimization operation are captured in the form of an object information signal responsive to a capture signal from the bus monitoring device. The data optimization attributes may be stored in either a trace cache of the target system or a memory of external trace capture equipment connected to the debug port, or a memory of the bus monitoring device. In providing the data optimization attributes external to the microcontroller, the data optimization attribute may be temporarily held by trace pins of a debug port of the microcontroller. The data optimization attributes may be extracted from the object information signal and processed by the external trace capture equipment or the bus monitoring device. By processing the data optimization attributes, pre-optimization write object values may be reconstructed.

Maintaining object information concurrent with data optimization for debugging

A computer chip including a data transfer network. The data transfer network comprises a plurality of communication ports and a plurality of modules. Each of the communication ports is directly connected to two or more other communication ports, and each of the communication ports is operable to communicate data. Each of the plurality of modules is coupled to at least one of the plurality of communication ports, and the plurality of modules are operable to communicate with each other through the communication ports. Furthermore, the plurality of communication ports are dynamically configurable to form two or more separate communication paths. The plurality of communication ports may be bi-directionally coupled and operable to communicate data with each other. The plurality of communication ports may also be dynamically configurable to form two or more communication rings. A first plurality of communication ports preferably comprise a first communication path, and a second plurality of communication ports comprise a second communication path. A first communication port in the first communication path is connected between two communication ports in the second communication path. The first communication port is then operable to transfer data between the two communication ports in the second communication path. The first plurality of communication ports and the second plurality of communication ports are also dynamically re-configurable to form two or more communication paths. The first plurality of communication ports and the second plurality of communication ports are preferably dynamically re-configurable to form one or more communication rings.

Data transfer network on a computer chip using a re-configurable path multiple ring topology

A computer chip including a data transfer network which comprises a plurality of communications links for transmitting data, a plurality of communication nodes, and a plurality of modules. Each of the communication nodes is directly connected to two or more other communication nodes through respective ones of the communications links. Each communication node is operable to communicate data over the respective one of the communications links. Each module is coupled to at least one of the communication nodes, and the modules are operable to communicate with each other through the communication nodes. The communication nodes are operable to create dynamic routes for the data transferred between any two or more of the plurality of modules over the respective ones of the communications links. The communication nodes form the dynamic routes based on statistical data on previous transmissions between the modules. Each communication node may include respective configuration logic for dynamically configuring the dynamic routes, and each configuration logic may include a memory for storing the statistical data on previous transmissions that passed through the respective communications node. The data transfer network may also comprise a routing module for controlling the dynamic routes based on statistical data. The routing module couples to each communication node and monitors the configuration logic. When present and functioning, the routing module adapts the dynamic routes based on an analysis of the statistical data. The statistical data includes one or more of the following for each respective transmission: priority, source module, destination module, number of data units, elapsed transfer time or minimum required transfer time, and total number of transmissions which pass through a given communications node.

Dynamically configured on-chip communications paths based on statistical analysis

A computer chip includes a data transfer network. The data transfer network comprises a backbone bus, a plurality of communication ports and a plurality of devices or modules each coupled to the backbone bus. Each of the devices includes or is coupled to one or more communication ports. Some of communication ports are operable to transmit and receive data on the backbone bus. Furthermore, the communication ports are interconnected in a ring topology forming a circular bus or a semi-circular bus. A subset of the communication ports may transmit and receive data on the circular bus or semi-circular bus. For the semi-circular bus, the communication ports are not coupled to form a complete ring topology. The communication ports may be operable to communicate with each other over the backbone bus and/or the circular bus. Each of the communication ports includes backbone bus interface logic, circular bus interface logic, one or more data transfer buffers and/or control logic. The communication ports are preferably able to transfer communications between the backbone bus, the circular bus and/or the modules.

Data transfer network on a computer chip utilizing combined bus and ring

A system and method for the streamlined execution of complex or repeating instructions. The method comprises creating a specialized instruction unit for executing a group of operations and then executing the group as they appear in an instruction stream. The system includes a programmable specialized instruction unit for executing the group of instructions as they appear in an instruction stream. The method comprises receiving a plurality of instructions, examining the plurality of instructions, identifying a subset of the plurality of instructions, creating a specialized instruction unit which is operable to execute the subset, and executing the subset in the special instruction unit upon an occurrence of the subset. Examining the plurality of instructions may occur at such times as compiling a computer program, performing an initialization procedure, or fetching or decoding instructions before execution. Identifying the subset includes selecting a series of instructions which require hardware external to the processor. Creating a specialized instruction unit includes programming a programmable logic or device. The method may also include identifying a second subset of the plurality of instructions, preparing a second specialized instruction unit which is operable to execute the second subset, and executing the second subset in the second specialized instruction unit. The specialized instruction unit is preferably embodied in a computer system comprising a decode unit, a plurality of registers coupled to the decode unit, a load/store unit coupled to the decode unit, a branch execute unit coupled to the decode unit, one or more arithmetic/logic units coupled to the decode unit, one or more specialized instruction units coupled to the decide unit, and a writeback unit coupled to the plurality of registers.

System and method for streamlined execution of instructions

An on-chip thermometer and methods for using the on-chip thermometer to measure a local temperature and to operate an integrated circuit. The on-chip thermometer comprises a clock circuit, a temperature responsive circuit, and a counter. The clock circuit operates at a fixed frequency and generates a fixed frequency clock signal. The temperature responsive circuit, when enabled, generates a signal dependent on local temperature. In response to receiving the clock signal, the temperature responsive circuit generates an output signal. The counter is coupled to receive the output signal from the temperature responsive circuit and the clock signal. The counter then generates a value indicative of a local temperature of the integrated circuit. A method of measuring a local temperature on an integrated circuit comprises generating a clock signal at a fixed frequency, providing the clock signal to a temperature responsive circuit, the temperature responsive circuit generating an oscillating signal comprising a plurality of oscillations dependent on a local temperature of the integrated circuit in response to receiving the clock signal, and counting the oscillations to generate a value indicative of the local temperature. On an integrated circuit including a plurality of processing modules located at respective locations with a plurality of on-chip thermometers, a task delegation module is coupled to each of the on-chip thermometers and the processing modules. Each on-chip thermometer generates a value indicative of a local temperature. The task delegation module receives output values from the on-chip thermometers and assigns processing tasks to the processing modules based on the local temperatures at each respective location.

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Austin, TX, United States of America

Gary Michael Godfrey