Netlogic Microsystems, Inc

Nortel Networks Corporation

Gary Michael Depelteau

David Walter Carr

John Edward Vincent

Ernst A Munter

James Leslie Watchorn

Tony Huang

Pascal De Wit

Abdulaziz Almulhem

George Frank Irwin

David Anthony Fisher

Abdulaziz S Almulhem

Osama Bahgat

Melhem I Chaar

James C McLaughlin

Sudhakar Reddy

Paul Fong-Yan Hung

A pipelined search engine supports a tree of search keys therein that utilizes span prefix masks to assist in longest prefix match (LPM) detection when the tree is searched. Each of a plurality of the span prefix masks encodes a prefix length of a search key to which the span prefix mask is associated and a value of another search key in the tree that is a prefix match to the search key to which the span prefix mask is associated.

Integrated search engine devices that support LPM search operations using span prefix masks that encode key prefix length

An integrated search engine device contains a pipelined arrangement of a plurality of search and tree maintenance sub-engines therein. This pipelined arrangement of sub-engines includes a hierarchical memory, which is configured to store a plurality of databases of search prefixes. These databases are arranged as a corresponding plurality of multi-way trees that span multiple levels of the hierarchical memory. The plurality of search and tree maintenance sub-engines are configured to respond to a database flush command by redesignating active nodes of a selected database within the hierarchical memory as free nodes using downstream and upstream communications between the plurality of search and tree maintenance sub-engines.

Integrated search engine devices having pipelined node maintenance sub-engines therein that support database flush operations

Methods of operating a search engine device include repeatedly reading next keys (and associated handles) from a database within the search engine device in order to identify and transfer some or possibly all of the contents of the database to another device (e.g., command host) requesting the database contents. An operation to read a next key includes: (i) searching a pipelined database within the search engine device with a first key to identify at least one key therein that is greater than the first key and then (ii) executing a next key fetch operation in the pipelined database to identify the next key from the at least one key. The next key and a handle associated with the next key are then retrieved from the search engine device (e.g., transferred to a command host).

Integrated search engine devices that support database key dumping and methods of operating same

A hierarchical memory includes a plurality of memory blocks, a common access bus coupled to the plurality of memory blocks, and a host bus interface coupled to the common access bus and configured to provide communication between an external host and the plurality of memory blocks over the common access bus. The memory further includes a Built-In Self Test (BIST) module coupled to the common access bus and configured to communicate with the plurality of memory blocks over the common access bus, and a test access interface coupled to the BIST main module and configured to receive test instructions and test data, to provide the test data to the BIST main module, and to configure the BIST main module in response to the test instructions. BIST operations are carried out in the memory blocks in response to BIST control signals and test data transmitted by the BIST module over the common access bus.

Combined processor access and built in self test in hierarchical memory systems

An integrated search engine includes a hierarchical memory configured to support a plurality of multi-way trees of search keys. These multi-way trees, which share a common root node, support respective databases of search keys. The child pointers associated with search keys within the common root node may be allocated at a single key level of granularity, which means that each search key within the common root node may be associated with a pair of child pointers when each search key within the common root node is associated with a different multi-way tree of search keys.

Integrated search engine devices having a plurality of multi-way trees of search keys therein that share a common root node

An integrated circuit search engine device supports a multi-way tree of search keys therein. The search engine device includes at least one multi-node sub-engine. The multi-node sub-engine includes a node processor and a plurality of columns of sub-nodes containing search keys. The node processor is configured to distribute an applied search key in parallel to each of the plurality of columns of sub-nodes in response to a search request. The node processor is also configured to receive and resolve corresponding sub-node search results from the plurality of columns of sub-nodes.

Integrated search engine devices that support multi-way search trees having multi-column nodes

Integrated circuit search engine devices include serially connected stages, a handle memory and a handle memory access manager. The stages store search keys in a multilevel tree of search keys. A first level stage is responsive to an input search key and a last level stage identifies a best match key for the input search key. The handle memory includes handle memory locations that store search result handles. The handle memory access manager searches the handle memory to retrieve a search result handle that corresponds to a best match key. The handle memory access manager refrains from modifying the handle memory in response to modify instructions during active periods of the handle memory when the handle memory is being searched. The handle memory access manager modifies the handle memory in response to the modify instructions during idle periods of the handle memory when the handle memory is not being searched. Related methods are also disclosed.

Handle memory access managers and methods for integrated circuit search engine devices

A search engine device includes a hierarchical memory that is configured to store a b-tree of search prefixes and span prefix masks (SPMs). These SPMs are evaluated during each search operation to identify search prefixes that match an applied search key yet reside at nodes of the b-tree that are not traversed during the search operation. The search engine device also includes handle memory. This handle memory is configured to support a respective handle memory block for each search prefix within each of a plurality of nodes of the b-tree that reside at a leaf parent level within the b-tree. Each of these handle memory blocks may have sufficient capacity to support one result handle per bit within a span prefix mask associated with a corresponding search prefix. In other cases, each of these handle memory blocks may have sufficient capacity to support only M+1 handles, where M is a positive integer corresponding to a quantity of search prefixes supported by each of a plurality of leaf nodes within the b-tree.

Integrated search engine devices that utilize hierarchical memories containing b-trees and span prefix masks to support longest prefix match search operations

A search engine includes a pipelined arrangement of a plurality of search and tree maintenance sub-engines therein, which are configured to support the performance of search operations on exclusively valid multi-way trees of search prefixes concurrently with the performance of update operations on the multi-way trees as they are being searched.

Integrated search engine devices having pipelined search and tree maintenance sub-engines therein that maintain search coherence during multi-cycle update operations

A handle allocation manager is provided for an integrated circuit search engine device that includes multiple stages of a multilevel tree of search keys and a handle memory. The handle allocation manager includes a handle availability memory that stores handle availability indicators to provide an indication of whether a handle is available for association with a key. A handle availability summary memory stores indicators for groups of handles and a block availability summary memory stores indicators for multiple groups of handle availability summary memories. The handle allocation manager can use these memories to search for a next available handle. Related methods are also provided.

Handle allocation managers and methods for integated circuit search engine devices

A pipelined search engine device, such as a longest prefix match (LPM) search engine device, includes a hierarchical memory and a pipelined tree maintenance engine therein. The hierarchical memory is configured to store a b-tree of search prefixes (and possibly span prefix masks) at multiple levels therein. The pipelined tree maintenance engine, which is embedded within the search engine device, includes a plurality of node maintenance sub-engines that are distributed with the multiple levels of the hierarchical memory. The search engine device may also include pipeline control and search logic that is distributed with the multiple levels of the hierarchical memory.

Integrated search engine devices having pipelined search and tree maintenance sub-engines therein that support variable tree height

A pipelined search engine device, such as a longest prefix match (LPM) search engine device, includes a hierarchical memory and a pipelined tree maintenance engine therein. The hierarchical memory is configured to store a b&#x2212;tree of search prefixes (and possibly span prefix masks) at multiple levels therein. The pipelined tree maintenance engine, which is embedded within the search engine device, includes a plurality of node maintenance sub-engines that are distributed with the multiple levels of the hierarchical memory. The search engine device may also include pipeline control and search logic that is distributed with the multiple levels of the hierarchical memory.

Integrated search engine devices having pipelined search and b-tree maintenance sub-engines therein

A packet switch has a switching unit (SU) for switching packets between network links and a computing unit (CU) connected to the SU through a network link for implementing software control functions over the SU. The SU is formed of different functional components interconnected by generic buses. The components communicate with one another using program data units (PDUs) that are formatted and transmitted according to a shared device protocol. The communication between the components occurs by placing PDUs in bus frames that are passed from component to component. Information is exchanged between the components by adding information to or dropping information from the fields of the PDUs, or by concatenating new fields to the PDUs, as the frames pass from component to component. By using a generic bus to implement PDU-based interconnections within the SU, all the components are forced to support a common interface. Changes to the implementations of any component's interface can thus be accommodated by changing the PDU format as opposed to changing the interfaces of connected components. The new packet switch architecture decouples the components on the switch so that they can be upgraded or otherwise modified independently of one another.

Message based packet switch based on a common, generic bus medium for transport

A scheduling apparatus, that can be used within a supertrunking capable Internet Protocol (IP) Forwarding (IPF) node, allows for efficient scheduling of packets for servicing after the packets are sorted into their proper order. The scheduling apparatus has a point and serve mechanism, a round-robin mechanism, and a starvation mechanism, and is to be used in situations where an IPF node is sorting and outputting multiple numbers of data streams. The point and serve mechanism directs two supertrunk pointers to the front packets of the particular data streams that the incoming packet segments correspond. The round-robin mechanism rotates a round-robin pointer between the front packets corresponding to all the different data streams. The starvation mechanism flags a data stream as starving if no packets have been scheduled after a predetermined number of times in which the round-robin pointer has been directed at the particular stream. Since only a limited number of packets can be scheduled for servicing at a time and each packet is not necessarily ready to be scheduled, the scheduling apparatus prioritizes the scheduling of the packets. First attempting to schedule the front packets selected by the point and serve mechanism, then the starvation mechanism, and finally the round-robin mechanism.

Scheduling technique for delayed queue service

Systems and methods for implementing ABR (available bit rate) flow control in ATM (asynchronous transfer mode switches are provided. A partitioned architecture a featuring standalone ABR processing subsystem advantageously allows components to be changed with little impact on the switch's overal design. Both end-to-end and VS/VD (virtual source/virtual destination) flow control systems are provided as are both configurations for switches which are either standalone or connected to a switching fabric.

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Gary Michael Depelteau