Bae Systems Information and Electronic Systems Integration Inc.

Gary M Madison

Joseph D Cali

Curtis M Grens

Richard L Harwood

Allen W Hairston

Kevin Grout

Randall M White

James M Meredith

Zachary D Schottmiller

Techniques are provided for a transimpedance amplifier (TIA). A TIA implementing the techniques according to an embodiment includes a pre-amplifier stage configured to amplify an input signal. The pre-amplifier stage includes a first P-channel metal oxide semiconductor field effect transistor (MOSFET) (P1), a second P-channel MOSFET (P2), a first N-channel MOSFET (N1), and a second N-channel MOSFET (N2), coupled in series. The gates of P1 and N2 are driven by the input signal. The output of the pre-amplifier stage is provided at a coupling between the drain of P2 and the drain of N1. The pre-amplifier stage also includes an active resistor network configured to provide a variable resistance based on a provided current bias generated from a gain control signal. The active resistor network is coupled between the gate of P1 and the drain of P2. The variable resistance is used to control the gain of the pre-amplifier stage.

High bandwidth transimpedance amplifier

A sample and hold amplifier output buffer with the low leakage of metal oxide semiconductor field effect transistors (MOSFET) combined with the linearity and dynamic range of silicon-germanium (SiGe) bipolar junction transistors (BJT). In one aspect, the present disclosure provides a sample and hold amplifier output buffer placing a MOSFET input device between the base and emitter of a high linearity SiGe BJT.

High dynamic range track and hold amplifier output stage using low voltage devices

A phase locked loop (PLL) control system includes a voltage-controlled oscillator (VCO) circuit including an inductor and a plurality of capacitors arranged in parallel with the inductor. Digitally enabling or disabling the capacitors in a thermometer coded manner via switches creates tuning states that provide additional frequency range, and each has a limited range of VCO frequency tuning. Slowly ramping the switched capacitance, by implementing the capacitor as a varactor, from one thermal code to the next, provides a wider continuous VCO frequency tuning range for use in the PLL. The slow transition between tuning states allows the PLL to remain in lock, useful under changing operating conditions. Specifically, under changing operating conditions, digital logic detects the PLL tuning control voltage approaching the edge of a VCO band and will add/reduce VCO capacitance effectively transitioning into the adjacent VCO band while the PLL maintains lock via its normal feedback loop.

Continuous tuning of digitally switched voltage-controlled oscillator frequency bands

A clock alignment system includes a first clock generator generating a first clock signal in a first clock domain and a second clock generator generating a second clock signal in a second clock domain slower than the first clock domain. A coarse delay-locked loop (DLL) generates third clock signals having corresponding phase offsets from the first clock signal, and a fine DLL generates a fourth clock signal by adjusting the phase of a selected one of the third clock signals. The second clock generator generates the second clock signal from the fourth clock signal. A phase detector compares phases of the first and second clock signals. A control circuit aligns the first and second clock signals by using the compared phases to select the third clock signal output by the coarse DLL, and control the phase adjustment by the fine DLL of this third clock signal.

Clock alignment system having a dual-loop delay-locked loop

The invention measures the frequency of a heterodyne laser radar (LADAR) system signal in the input cell of a focal plane array (FPA). Embodiments amplify the return signal, and drive it into a counter for a fixed period of time. The frequency is the number of counts divided by the count time. An example design amplifier amplifies the return of a single photon response of an avalanche photodiode with a gain of 100 into a digital signal level at a 200 MHz rate with only 84 &#x3bc;W, demonstrating the feasibility of the approach.

Frequency measurement focal plane array input circuit

An input clamping circuit of a photo detector preamplifier is activated when an input transistor is turned off by an input overload, and the drain voltage of the input transistor is pulled toward ground by a current source. Even with extreme overloads, the operating conditions (Vgs and Id) of the input transistor remain within normal range. During normal operation, the clamping circuit is biased completely off, and has essentially no effect on circuit performance. Since the input FET itself, rather than a separate device, detects the onset of an overload, significantly improved clamping performance is realized without adding additional circuit complexity. The input transistor can be a FET. The preamplifier can be a cascode preamplifier. The clamping circuit can include a clamping FET or other clamping transistor gated by the input transistor drain. In embodiments, the clamping circuit increases current requirements of the preamplifier by no more than 25%.

Anti-blooming circuit for integrating photodiode pre-amplifiers

Circuitry is disclosed that can be used, for example, in a readout circuit of an active imaging or other sensing application. The circuitry can be configured, for instance, for increasing the gain of a differential amplifier non-inverting leg used to drive the inverting output by means of a current-source load. In some example embodiments, the circuitry is suitable for use in a focal plane array input unit cell and can be implemented, for instance, as a relatively low power amplifier with high gain, bandwidth and output current-sinking capability (in some embodiments; current sourcing in others) sufficient to respond to very fast photo-diode (e.g., standard or e-APD) detector signals. The amplifier circuitry can be used with other transducer arrays and is not intended to be limited to imaging applications.

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Waltham, MA, United States of America

Gary M Madison