Micron Technology Incorporated

Round Rock Research, LLC

Oce Usa, Inc.

Gary M Johnson

Tyler J Gomm

Ward D Parkinson

Thomas M Trent

Wen-Foo Chern

Leland R Nevill

Tyler A Lowrey

Kevin G Duesman

Stanley N Protigal

Zhitong Chen

Wen Qian Li

Kang Yong Kim

Jon P Busack

John R Brustad

Jeremy J Albrecht

David L Pinney

Steven C Johnson

Eric J Luttmann

Steve Casper

Richard D Newman

Matt Stephenson

Frank Hartmann

Ray Asbury

Dennis W Hicks

Lisa O'Toole

Richard R Clem

Greg Roberts

David Hay

Web-Foo Chern

Chris Gyllenskog

Eric Nguyen

M Becerra Matthew

Ghassan Sakakine

Matthew M Becerra

Jonathan Covach

Clock circuits and apparatus containing such are useful in clock synchronization and skew adjustment. Such clock circuits may include a delay line coupled to receive an input signal, wherein the delay line comprises a plurality of delay elements, and wherein at least two delay elements of the plurality of delay elements differ in unit time delay. Such clock circuits may further include a phase detector coupled to receive the input signal and a signal generated from an output signal of the delay line. The phase detector may be configured to compare the input signal to the generated signal and to adjust a length of the delay line to synchronize the input signal and the generated signal.

Clock circuits and apparatus containing such

Apparatus for synchronizing signals. For memory devices, such as SDRAMs, implementing a synchronization device to synchronize one signal, such as an external clock signal with a second signal, such as a data signal, tuning elements may be provided at various points in the signal path of the synchronization device. The tuning elements are designed to be identical, such that a single design may be used to a signal mismatch that is produced in either direction, using a single design. The tuning elements may be implemented to provide uniformity in the access time through a range of conditions, such as drain voltages and temperatures.

Synchronization devices having input/output delay model tuning elements in signal paths to provide tuning capabilities to offset signal mismatch

Clock synchronization and skew adjustment circuits that utilize differing unit delay elements in their delay lines in either a graduated or a stepped unit time delay arrangement are for synchronizing with a clock signal. These graduated or a stepped unit time delays allow reduction in the number of the fine unit delay elements of the delay lines by placing a fine delay element granularity at the most critical timings to sense and adjust for the portion of the clock signal time period that are high speed or critical.

Method and apparatus for synchronizing with a clock signal

Methods and apparatus for synchronizing with a clock signal

An apparatus and method for generating phase-related clocks are disclosed. A clock input is delayed by an alignment magnitude to generate a first phase signal. The first phase signal is delayed by the phase alignment magnitude to generate a first phase delay signal. The clock input is delayed by a phase delay magnitude to generate a second phase signal and the second phase signal is delayed by about the phase delay magnitude to generate a last phase delay signal. A phase difference is detected between the first phase delay signal and the last phase delay signal and adjustments are made to at least one of the phase delay magnitude and the alignment magnitude.

Method and apparatus for digital phase generation for high frequency clock applications

A method and apparatus is provided for providing a fine delay by switching on a capacitor delay. A coarse delay and/or a fine delay are implemented upon a reference signal based upon a phase shift between the reference signal and a feedback signal. A fine delay is implemented upon the reference signal based upon a phase shift between the reference signal and a feedback signal. Providing the fine delay includes switching on a capacitive delay. A synchronized output signal is generated based upon the fine delay.

Switched capacitor for a tunable delay circuit

Methods, devices, and systems are disclosed for a delay locked loop. A delay locked loop may comprise a delay line configured to receive a reference clock signal and output a delayed clock signal. The delay locked loop may also comprise a feedback loop including a frequency divider operably coupled to the delayed clock signal and configured to generate a frequency divided clock signal. Furthermore, the delay locked loop may include a phase detector configured to receive the reference clock signal and the frequency divided clock signal having a frequency less than that of the reference clock signal. Additionally, the phase detector may be configured to measure a phase difference of the reference clock signal and the frequency divided clock signal upon receipt of an active edge of the frequency divided clock signal.

Methods, devices, and systems for a delay locked loop having a frequency divided feedback clock

Clock synchronization and skew adjustment circuits are described that utilize varying unit delay elements in their delay lines in either a graduated or a stepped unit time delay arrangement, allowing a reduced circuit implementation and improved lock characteristics. These graduated or a stepped unit time delays allow reduction in the number of the fine unit delay elements of the delay lines by placing a fine delay element granularity at the most critical timings to sense and adjust for the portion of the clock signal time period that are high speed or critical. This allows clock synchronization and skew adjustment circuits to be implemented in an optimized manner that exhibits a reduced overall circuit size and power consumption, while having improved lock characteristics over a wide range of frequencies.

Graduated delay line for increased clock skew correction circuit operating range

A phase detector generates a first output signal if a feedback clock signal leads a reference clock signal by more than a first time. The phase detector generates a second output signal if the feedback clock signal lags the reference clock signal by more than a second time. If the feedback clock signal either leads the reference clock signal by less than the first time or lags the reference clock signal by less than the second time, neither output signal is generated. The phase detector may be used in a delay-lock loop in which the first and second output signals increase or decrease a delay of the reference clock signal by respective first and second delay increments. In such case, the each of the first and second delay increments should be less than the sum of the first and second times.

Phase detector and method having hysteresis characteristics

A delay-locked loop (DLL) with feedback compensation is provided to increase the speed and accuracy of the DLL. After the variable delay line of the DLL is adjusted to minimize phase error, multiple clock cycles may be required before the adjusted signal is fed back to the phase detector. During this time, a signal replicating the adjusted signal is temporarily fed to the phase detector until the adjusted signal reaches the phase detector.

Delay-locked loop with feedback compensation

A method and apparatus for synchronizing signals. For memory devices, such as SDRAMs, implementing a synchronization device to synchronize one signal, such as an external clock signal with a second signal, such as a data signal, tuning elements may be provided at various points in the signal path of the synchronization device. The tuning elements are designed to be identical, such that a single design may be used to a signal mismatch that is produced in either direction, using a single design. The tuning elements may be implemented to provide uniformity in the access time through a range of conditions, such as drain voltages and temperatures.

Synchronization device with delay line control circuit to control amount of delay added to input signal and tuning elements to receive signal form delay circuit

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Boise, ID, United States of America

Gary M Johnson