Sandisk Technologies Inc.

Palantir Technologies Inc.

Kioxia Corporation

Gary Lin

Robert David Selinger

Chaoyang Wang

Paul A Lassa

Matthew Davidson

Daniel Edward Tuers

Matthew Elkherj

Lucas Lemanowicz

Andrew Pettit

Ashwin Sreenivas

Daniel Spangenberger

Joules Nahas

Tinlok Pang

Yehonatan Steinmetz

Robert G Gugel

Robert Jackson

Adam Schexnayder

Umang Thakkar

Natasha Armbrust

Tomer Kremerman

Sergey Anatolievich Gorobets

Abhijeet Manohar

Yoav Weinberg

Rajeev Nagabhirava

Damian Pablo Yurzola

Girish Desai

Avadhani Shridhar

William Guthrie

Milton Lourenco Barrocas

Matt Davidson

Aruna Gutta

Tiruvur Radhakrishna Ramesh

Senthilkumar Diraviam

Various implementations described herein relate to systems and methods for a solid state drive (SSD) that includes a first controller and a NAND package. The NAND package includes a plurality of dies grouped into a plurality of subsets. The NAND package includes a second controller operatively coupled to each of the plurality of subsets via a corresponding one of a plurality of parallel mode channels. The first controller is operatively coupled to the NAND package via a serial link.

Multiple parallel mode flash channels with serial link

Systems and methods are disclosed for systems and user interfaces for rapid analysis of viewership information. One of the methods includes accessing databases storing viewership information associated with segments, with each segment being associated with common features of viewers. Measures of association between the segment and content items are maintained for each segment. An interactive user interface is presented via a user device, the interactive user interface enabling creation of a customized viewing audience. The interactive user interface receives user input indicating a segment, identifies similar segments based on associations between features of the segment and of other segments, and presents the identified segments. Analysis information associated with the segments is presented for at least one of the one or more segments, with the segments being included in the customized viewing audience.

System and user interfaces for rapid analysis of viewership information

The various implementations described herein include systems, methods and/or devices for reading data stored in a storage device. In one aspect, read commands are executed, each command for reading a requested logical group of data from a specified logical address comprising one or more logical portions. A first physical location in the storage device corresponding to the logical address is identified from a mapping table, and data is read. In accordance with a determination that the first physical location stores less than all of the logical group of data, a second physical location is identified based on information contained within the data from the first physical location, and data is read from the second physical location. Data read from the one or more physical locations is decoded to produce the requested logical group of data, which is then returned.

Reading logical groups of data from physical locations in memory using headers

The various implementations described herein include systems, methods and/or devices for storing data in a storage device. In one aspect, commands are executed, each command for storing in a storage device a logical group of data comprising one or more logical portions and having a logical address. For each command, in accordance with a determination that a remaining capacity of a first physical memory portion is less than a threshold capacity, data is stored for a head logical portion in a first physical location corresponding to the first physical memory portion. Furthermore, data is stored for a tail logical portion in a second physical location corresponding to a second physical memory portion. Mapping entries are stored in a mapping table, where the mapping entries map the corresponding logical address to at least the first physical location in the storage device.

Writing logical groups of data to physical locations in memory using headers

A storage module may include a non-volatile memory module and a controller that communicates with the non-volatile memory module using a communications bus. In response to receipt of a host command, the controller may generate one or more sets of context commands for communication of data on the communications bus between the controller and an area of memory. The controller may execute the sets of context commands in a cache sequence. During execution of the context commands in the cache sequence, the controller may determine an opportunity window that occurs after execution of a context command of a prior set and before execution of a context command of a current set, during which the controller may utilize the communications bus.

Delayed automation to maximize the utilization of read and write cache

A storage module may include a controller that has hardware path that includes a plurality of hardware modules configured to perform a plurality of processes associated with execution of a host request. The storage module may also include a firmware module having a processor that executes firmware to perform at least some of the plurality of processes performed by the hardware modules. The firmware module performs the processes when the hardware modules are not able to successfully perform them.

Hardware and firmware paths for performing memory read processes

The embodiments described herein provide a method and controller for performing a sequence of commands. In one embodiment, a controller receives a command from a host to perform a memory operation in a flash memory device, wherein the command comprises at least one bit that indicates whether the command is a stand-alone command or is part of a sequence of commands. The controller analyzes the at least one bit to determine whether the at least one bit indicates that the command is a stand-alone command or is part of a sequence of commands. If the at least one bit indicates that the command is a stand-alone command, the controller performs the command. If the at least one bit indicates that the command is part of a sequence of commands, the controller performs the command as part of the sequence of commands.

Method and controller for performing a sequence of commands

Apparatus and methods implemented therein are disclosed for communicating with flash memories. The apparatus comprises a flash interface module and a processor in communication with the flash interface module. The flash interface module is configured for communication with a first and second flash bank. The processor is configured to generate a plurality of command sequences in response to receiving a plurality of flash commands from a host system. Each of the plurality of command sequences corresponds to a respective one of the plurality of flash commands. Some of the plurality of command sequences comprises a first portion and a second portion and each of the first portion and second portion are atomic. The processor associates each of the plurality of command sequences with a priority, and via the flash interface module, selects one of the plurality of the command sequences based on the priority associated with the one of the plurality of the command sequences and transmits sequentially the first portion of the one of the plurality of the command sequences to either one of the first flash bank or the second flash bank.

Method and system for communicating with non-volatile memory

Systems and methods implemented therein are disclosed for communicating data in a flash memory system. The system comprises a memory system, a data path manager (DPM) and a memory controller. The memory system is configured to receive a flash command from a host processor. In response to receiving the flash command, the memory system is configured to communicate a flash command sequence to one of the first flash device or the second flash device. Separately, the data path manager (DPM) is configured to select a subset of logical data paths from a set of logical data paths. Data is communicated between the memory controller and either one of the first flash device or the second flash device via the subset of logical data paths.

Method and system for communicating with non-volatile memory via multiple data paths

Systems and methods implemented therein are disclosed for communicating data between a memory controller and a first flash device. The system comprises a memory controller having a flash interface module. The memory controller is adapted to be communicatively coupled to a host system. The memory controller configured to receive a template. The template comprises a first set of resources for communicating data between the memory controller and the flash device and based on the template. The memory controller is adapted to configure the first set of resources for communicating data between the memory controller and the first flash device. The flash interface module is communicatively coupled to the memory controller. The flash interface module is configured to communicate data between the memory controller and the first flash device via the first set of resources.

Method and system for using templates to communicate with non-volatile memory

The embodiments described herein provide a method and controller for performing a copy-back command. In one embodiment, a controller receives the data and error correction code associated with a copy-back operation from at least one flash memory device. The controller determines if the error correction code indicates there is an error in the data. If the error correction code does not indicate there is an error in the data, the controller sends a destination address and copy-back program command received from a host to the at least one flash memory device. If the error correction code indicates there is an error in the data, the controller corrects the data and sends the destination address, the corrected data, and a program command to the at least one flash memory device. Additional embodiments relate to modifying data during the copy-back operation.

Method and controller for performing a copy-back operation

A non-volatile memory system includes a memory controller that receives commands from a host and identifies commands that can be executed in parallel. The order in which commands are received is recorded so that responses may be provided to the host in the same order in which the commands were received.

Memory system with command queue reordering

Buffer memory reservation techniques for use with NAND flash memory include dynamically reserving regions of the buffer memory, responsive to a read/write request. Where the read/write request includes a plurality of data transfer requests, following completion of a data transfer request, the reserved buffer space may be recycled for use in a further data transfer request or for other purposes. During fulfillment of a read request, a buffer region is reserved from a larger buffer pool for a time period significantly smaller than the time required to execute a sense operation associated with the read request. The reserved buffer region may be reused for unrelated processes during execution of the sense operation.

Buffer memory reservation techniques for use with a NAND flash memory

Disclosed are apparatus and techniques for managing power in a memory system having a controller and nonvolatile memory array. In one embodiment, prior to execution of each command with respect to the memory array, a request for execution of such command is received with respect to the memory array. In response to receipt of each request for each command, execution of such command is allowed or withheld with respect to the memory array based on whether such command, together with execution of other commands, is estimated to exceed a predetermined power usage specification for the memory system.

Growing community of inventors

San Jose, CA, United States of America

Gary Lin