Cisco Technology, Inc.

Telebit Corporation

Gary Leon Cohen

Scott Kingsley Smader

Ken Yeung

An arbiter uses a history based bus arbitration scheme to more fairly allocate a shared resource among multiple devices. The arbiter uses a history queue to dynamically update the priorities of the devices using the shared resource, and makes the grant decision in a single calculation using the combination of the history queue and requests from bidding devices. The priority for granting master to each device is dynamically modified so that the least recently serviced requestor will be granted the shared resource. A hidden arbitration scheme provides more fair history based resource allocation. A bus retry scheme demotes priority for processing devices that are assigned bus master but do not perform bus operations within a predetermined number of clock cycles. The arbiter also prevents bus grants during hot swap operations.

History-based bus arbitration with hidden re-arbitration during wait

A memory control system and method for controlling access to a global memory. The global memory has multiple memory banks coupled to a memory bus. Multiple memory controllers are coupled between processing devices and the memory bus. The memory controllers control access of the processing devices to the multiple memory banks by independently monitoring the memory bus with each memory controller. The memory controllers track which processing devices are currently accessing which memory banks. The memory controllers overlap bus transactions for idle memory banks. The bus transactions include a control bus cycle that initially activates the target memory bank and data bus cycles that transfer data for previously activated memory banks. A control bus arbiter coupled to the memory bus grants activation of the multiple memory banks according to a first control bus request signal and a separate data bus arbiter operating independently of the control bus arbiter grants data transfer requests according to a second data bus request signal.

Memory control system and method utilizing distributed memory

An interface for connecting data-terminal-equipment (DTE) to a range of data-communication-equipment (DCE) using a multiplicity of interface standards is provided. The interface includes a DTE panel connector and a plurality of line drivers and receivers and associated electronics to select predetermined ones of the plurality of receivers and drivers for use by the DTE when cables having a predetermined configuration, corresponding to the supported interface standards, are attached. The cables connect the appropriate drivers and receivers of the DTE with the corresponding receivers and drivers, respectively, of the DCE. Additionally the cables also contain termination devices and a selection mechanism to select which drivers and receivers are to be used by the DTE to communicate with the receivers and drivers, respectively, being used by the DCE.

Serial communications interface that supports multiple interface

An interface for connecting data-terminal-equipment (DTE) to a range of data-communication-equipment (DCE) using a multiplicity of interface standards is provided. The interface includes a DTE panel connector and a plurality of line drivers and receivers and associated electronics to select predetermined ones of the plurality of receivers and drivers for use the DTE when cables having a predetermined configuration, corresponding to the supported interface standards, are attached. The cables connect the appropriate drivers and receivers of the DTE with the corresponding receivers and drivers, respectively, of the DCE. Additionally the cables also contain termination devices and a selection mechanism to select which drivers and receivers are to be used by the DTE to communicate with the receivers and drivers respectively, being used by the DCE.

Growing community of inventors

Sunnyvale, CA, United States of America

Gary Leon Cohen