Texas Instruments Corporation

Mitsubishi Denki Kabushiki Kaisha

Texas Incorporated Incorporated

Gary L Swoboda

Manisha Agarwala

Robert A McGowan

Oliver P Sohm

Bryan Joseph Thome

Brian Cruickshank

Douglas E Deao

David R Matt

Martin D Daniels

Lewis Nardini

Peter N Ehlig

Joseph A Coomes

Timothy David Anderson

Kevin C McDonough

Jagadeesh Sankaran

Leland J Szewerenko

Karthik Ramana Sankar

Mark R Hammes

Joseph R Zbiciak

Abhijeet Ashok Chachad

Keith Balmer

Raguram Damodaran

Michael D Asal

Jason Lynn Peck

Surendar S Magar

Jose Luis Flores

John M Johnsen

Anthony J Lell

Maria B H Gill

Jason A Jones

Lee Alan Larson

Henry R Hoar

Deborah C Keil

Craig D McLean

Nick Ing-Simmons

Jiuling Liu

Richard D Simpson

Alan Davis

Iain Craig Robertson

Nicholas K Ing-Simmons

Edward R Caudel

Jeffrey D Bellay

Amitabh Menon

Eric J Stotzer

Karthikeyan Rajan Madathil

Paul Arthur Gingrich

Nat Seshan

Antony W Leigh

Madathil R Karthikeyan

Jonathan Dzoba

Edmund Sim

Kenneth E Aron

Sambandam Manohar

Mark B Rix

John W Mayn

Roland R Hoar

Robert A Mcgowan

Douglas Deao

Deborah Keil

Robert Mcgowan

Leland Szwewrenko

Craig Mclean

A method comprises a system comprising a host device coupled to a first remote device actively operating according to a state diagram that the host device and all remote devices follow during operation of the system. The method further comprises powering up a second remote device while the host device and first remote device are actively operating according to the state diagram. The second remote device waits for a synchronization point sequence. Upon detecting the synchronization point sequence, the second remote device implements a predetermined feature set and synchronizes itself to the state diagram at a common point as the host device and first remote device.

Synchronizing a device that has been power cycled to an already operational system

The present disclosure describes systems and methods for controlling access to secure debugging and profiling features of a computer system. Some illustrative embodiments include a system that includes a processor, and a memory coupled to the processor (the memory used to store information and an attribute associated with the stored information). At least one bit of the attribute determines a security level, selected from a plurality of security levels, of the stored information associated with the attribute. Asserting at least one other bit of the attribute enables exportation of the stored information from the computer system if the security level of the stored information is higher than at least one other security level of the plurality of security levels.

Systems and methods for controlling access to secure debugging and profiling features of a computer system

Operating state machine controllers after powering, decoupling, monitoring, coupling communications

Control events may be signaled to a target system having a plurality of components coupled to a scan path by using the clock and data signals of the scan path. While the clock signal is held a high logic level, two or more edge transitions are detected on the data signal. The number of edge transitions on the data signal is counted while the clock signal is held at the high logic state. A control event is determined based on the counted number of edge transitions on the data signal after the clock signal transitions to the low logic state.

TCKC/TMSC counter, gating circuitry for selection, deselection, technology specific outputs

Performing series equivalent scans spanning a plurality of scan technologies in a complex scan topology may be performed by performing shift operations in the complex scan topology while only one branch of the complex scan topology connectivity is enabled, and performing capture and update operations in parallel while scan topology connectivity of two or more of the plurality of scan technologies is enabled.

Series equivalent scans across multiple scan topologies

An integrated circuit is provided with a voltage sag detector (VSD) within the integrated circuit package. The VSD is coupled to a voltage reference and to the power distribution bus within the integrated circuit. The VSD has an output for indicating when a voltage level on the power distribution bus sags below a voltage level provided by the voltage reference.

Detecting power supply sag in an integrated circuit

Pipeline processor data and attribute register, secure emulation logic, gating

Monitoring communication link in powered-up device for synchronization point sequence

A system and method for sharing a communications link between multiple protocols is described. A system includes a communications interface configured to exchange information with other systems using at least one of a plurality of protocols; a protocol select register that stores a value that selects a protocol from among the plurality of protocols to become an active protocol; and a state machine accessible to the communications interface, the state machine used to control the exchange of information through the communications interface according to the active protocol. The active protocol is used by the communications interface to exchange information while the remaining protocols of the plurality of protocols remain inactive. The state machine sequences through a series of states that cause the communications interface to operate according to the active protocol, and that are designated as inert sequences under the remaining protocols.

Adapter circuitry with link and system interfaces to core circuitry

TCK, TMS(C) clock, gating circuitry providing selection and deselection outputs

A system comprises a plurality of components, scan chain selection logic coupled to the components, and override selection logic coupled to the scan chain selection logic. The scan chain selection logic selects various of the components to be members of a scan chain under the direction of a host computer. The override selection logic detects a change in the scan chain and, as a result, blocks the entire scan chain from progressing.

Scan path only one-bit scan register when component not selected

Pipeline processor execution stages, secure emulation logic, gating debug/profile output

A method comprises a system comprising a host device coupled to a first remote device actively operating according to a state diagram that the host device and all remote devices follow during operation of the system. The method further comprises powering up a second remote device while the host device and first remote device are actively operating according to the state diagram. The second remote device determines whether to initialize to a standard protocol or to an advanced protocol. Upon determining to initialize to the advanced protocol, the second remote device then waits for a synchronization point sequence.

Operating two tap system after detecting shared bus synchronization sequence

Growing community of inventors

Sugar Land, TX, United States of America

Gary L Swoboda