Cirrus Logic Inc.

Credence Systems Corporation

Gary L Schaps

Geary L Leger

Peter R Carpenter

Bhoopal R Benjaram

Brian J Arkin

John A Wishneusky

John Andrew Wishneusky

An algorithmic pattern generator for generating an output vector on each pulse of a clock signal includes a vector memory for storing a vector and an accompanying repeat number at each of several addresses. On each of N consecutive clock signal pulses, a repeat processor appends an instance of a vector read out of the vector memory to the pattern generator's output vector sequence. An instruction processor causes the instruction memory to read out instructions and responds to each instruction by telling the instruction processor to signal the address counter to supply the starting address to the vector memory and to thereafter periodically increment the starting address for M consecutive clock signal cycles. When appending N instances of each vector to the pattern generator output sequence, the repeat processor inhibits the address counter from incrementing its output address for N&minus;1 cock signal cycles.

High-speed algorithmic pattern generator

A method and arrangement for performing direct memory access in a computer system having multi-channel direct memory access (DMA) is provided with a host computer having a main memory and a processor that runs software, a system interface bus coupling the host computer and the main memory, and multiple DMA controllers, on separate chips, coupled to the system interface bus. These multiple DMA controllers provide the system with multiple input/output (I/O) channels. A common buffer pool having a plurality of buffers is accessible to each of the multiple channels for buffering data transferred to or from the host computer. A status queue is also provided, with each entry in the status queue indicating whether a corresponding buffer from the common pool of buffers is a free buffer available for use by one of the DMA channels in a DMA transaction. The status queue is searched for an entry in the status queue which indicates whether its corresponding buffer is a free buffer, when a DMA transaction is to occur over one of the DMA channels. When a free buffer is found, the entry in the status queue and the free buffer are claimed by the DMA channel. The starting address of the free buffer is then determined and data is buffered within the free buffer.

DMA controller arrangement having plurality of DMA controllers and

A method and arrangement for performing direct memory access in a computer system having multi-channel direct memory access (DMA) is provided with a host computer having a main memory and a processor that runs software, a system interface bus coupling the host computer and the main memory, and a multi-channel DMA controller arrangement coupled to the system interface bus and having multiple input/output (I/O) channels. A common buffer pool having a plurality of buffers is accessible to each of the multiple channels for buffering data transferred to or from the host computer. A status queue is also provided, with each entry in the status queue indicating whether a corresponding buffer from the common pool of buffers is a free buffer available for use by one of the DMA channels in a DMA transaction. The status queue is searched for an entry in the status queue which indicates whether its corresponding buffer is a free buffer, when a DMA transaction is to occur over one of the DMA channels. When a free buffer is found, the entry in the status queue and the free buffer are claimed by the DMA channel. The starting address of the free buffer is then determined and data is buffered within the free buffer.

DMA controller having multiple channels and buffer pool having plurality

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Fremont, CA, United States of America

Gary L Schaps