Sun Microsystems, Inc.

Celerity Computing

Gary L Riddle

Andrew E Phelps

Patricia Shanahan

James E Kocol

Nicholas E Aneshansley

Andrew Jackson McCrocklin

Thomas P Van Wormer

James J Whelan

Jeffrey P Anderson

A method for communicating transactions includes providing an interconnect having a plurality of ports for communicating transactions between a plurality of domains in a computing system is provided. Each port is associated with a subset of the domains. The interconnect includes a first signal path for transmitting a first portion of the transaction and a second signal path for transmitting a second portion of the transaction. A transaction issued from a port associated with more than one of the domains is identified. An error in one of the first and second portions of the transaction is identified. The transaction is canceled responsive to identifying the error. A computing system for communicating transactions includes first and second devices. The first device is adapted to receive a first portion of a transaction. The second device is adapted to receive a second portion of the transaction in lockstep with respect to the first device. The first and second devices are further configured to identify an error in one of the first and second portions of the transaction, respectively, and the one of the first and second devices that identifies the error is further configured to send a notification signal to the device associated with the other of the first and second portions of the transaction responsive to identifying the error.

Method and apparatus for arbitrating transactions between domains in a computer system

A direct-execution microprogrammable microprocessor system uses an emulatory microprogrammable microprocessor for direct execution of microinstructions in main memory through a microinstruction port. A microinstruction cache with a microinstruction address extension unit serving to communicate microinstructions from the main memory to the microprogrammable microprocessor. Virtual main memory accesses occur through a system multiplexer. A virtual address extension unit and a virtual address bus provide extension and redefinition of the main memory address space of the microprogrammable microprocessor. The system also uses a context switching stack cache and an expanded address translation cache with the microprogrammable microprocessor having a reduced and redefined microinstruction set with a variable microinstruction cycle.

Direct-execution microprogrammable microprocessor system

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Gary L Riddle