International Business Machines Corporation

Globalfoundries Inc.

Other

Gary L Milo

Max Gerald Levy

David C Thomas

Edward Crandal Cooney, Iii

Qizhi Liu

Robert K Leidy

Jeffrey P Gambino

Arne Watson Ballantine

Timothy Dooling Sullivan

Ronald A Warren

Matthew D Moon

Anthony C Speranza

Scott Alan Estes

Mark D Levy

Emily E Fisch

Steven S Williams

Thomas W Weeks

Steven M Shank

Zhong-Xiang He

Xiao Hu Liu

Thomas L McDevitt

William Joseph Murphy

Richard Stephen Graf

Mark Levy

Dinh Dang

Brett T Cucci

David A DeMuynck

Sarah A McTaggart

Yutong Wu

Patrick S Spinney

Thomas C Lee

John C Hall

Kenneth A Bandy

Stuart D Cheney

Melissa J Roma

Jeffrey L Thompson

Brian P Conchieri

Aspects of the present disclosure include a test structure that includes two or more devices. Each device includes a wire disposed within a dielectric and a first via disposed over the wire and in electrical contact with the wire. Each device includes a test pad electrically connected to the first via and a polysilicon resistor electrically connected to the wire. Each of the polysilicon resistors of the two or more devices are electrically tied together. A method for forming the interconnect structure to be used for testing is also provided.

Test structure for monitoring interface delamination

Embodiments disclose a method of fabrication and a semiconductor structure comprising a Metal-insulator-metal (MIM) capacitor. The method of fabrication includes depositing a first conductive material on a semiconductor substrate. A first dielectric material is deposited on the first conductive material. A second conductive material is deposited on the first dielectric material. The top plate is formed by etching the second conductive material. The bottom plate is formed by etching a portion of the first conductive material. At least one opening is formed in the first dielectric layer down to the first conductive material.

Semiconductor device with metal extrusion formation

A method including forming a first metal wire in a first dielectric layer, the first metal wire including a first vertical side opposite from a second vertical side; and forming a second metal wire in a second dielectric layer above the first dielectric layer, the second metal wire including a third vertical side opposite from a fourth vertical side, where the first vertical side is laterally offset from the third vertical side by a first predetermined distance, and the second vertical side is laterally offset from the fourth vertical side by a second predetermined distance, where the first metal wire and the second metal wire are in direct contact with one another.

Metal wires of a stacked inductor

Aspects of the present invention relate to a controlled metal extrusion opening in a semiconductor structure. Various embodiments include a semiconductor structure. The structure includes an aluminum layer. The aluminum layer includes an aluminum island within the aluminum layer, and a lateral extrusion receiving opening extending through the aluminum layer adjacent the aluminum island. The opening includes a lateral extrusion of the aluminum layer of the semiconductor structure. Additional embodiments include a method of forming a semiconductor structure. The method can include forming an aluminum layer over a titanium layer. The aluminum layer includes an aluminum island within the aluminum layer. The method can also include forming an opening extending through the aluminum layer adjacent the aluminum island within the aluminum layer. The opening includes a lateral extrusion of the aluminum layer of the semiconductor layer.

Controlled metal extrusion opening in semiconductor structure and method of forming

Various embodiments include a silicon-based optical waveguide structure locally on a bulk silicon substrate, and systems and program products for forming such a structure by modifying an integrated circuit (IC) design structure. Embodiments include implementing processes of preparing manufacturing data for formation of the IC design structure in a computer-implemented IC formation system, wherein the preparing of the manufacturing data includes inserting instructions into the manufacturing data to convert an edge of the at least one shape from a &#x3c;110&#x3e; crystallographic direction to a &#x3c;100&#x3e; crystallographic direction.

Silicon waveguide structure with arbitrary geometry on bulk silicon substrate, related systems and program products

Disclosed is a trench formation technique wherein an opening having a first sidewall with planar contour and a second sidewall with a saw-tooth contour is etched through a semiconductor layer and into a semiconductor substrate. Then, a crystallographic wet etch process expands the portion of the opening within the semiconductor substrate to form a trench. Due to the different contours of the sidewalls and, thereby the different crystal orientations, one sidewall etches faster than the other, resulting in an asymmetric trench. Also disclosed is a bipolar semiconductor device formation method that incorporates the above-mentioned trench formation technique when forming a trench isolation region that undercuts an extrinsic base region and surrounds a collector pedestal. The asymmetry of the trench ensures that the trench isolation region has a relatively narrow width and, thereby ensures that both collector-to-base capacitance Cand collector resistance Rare minimized within the resulting bipolar semiconductor device.

Formation of an asymmetric trench in a semiconductor substrate and a bipolar semiconductor device having an asymmetric trench isolation region

Various embodiments include managing metal densities in kerf sections of an integrated circuit (IC) wafer. In some embodiments, a method includes: forming an integrated circuit (IC) wafer including a wafer kerf region, the wafer kerf region having a metal density of less than approximately 0.5 percent relative to a total density of the wafer kerf region.

Methods of managing metal density in dicing channel and related integrated circuit structures

A semiconductor device and a method of fabricating the same, includes vertically stacked layers on an insulator. Each of the layers includes a first dielectric insulator portion, a first metal conductor embedded within the first dielectric insulator portion, a first nitride cap covering the first metal conductor, a second dielectric insulator portion, a second metal conductor embedded within the second dielectric insulator portion, and a second nitride cap covering the second metal conductor. The first and second metal conductors form first vertically stacked conductor layers and second vertically stacked conductor layers. The first vertically stacked conductor layers are proximate the second vertically stacked conductor layers, and at least one air gap is positioned between the first vertically stacked conductor layers and the second vertically stacked conductor layers. An upper semiconductor layer covers the first vertically stacked conductor layers, the air gap and the second plurality of vertically stacked conductor layers.

Structure and method for reducing vertical crack propagation

In a process using a hot phosphoric acid etchant () to etch silicon nitride on a semiconductor wafer () submerged in a tank () of the etchant (), a recirculating path is established for the etchant (). A porous filter () is coated with silicon nitride and installed in the recirculating path. As the etchant () in the recirculating path flows through the porous filter (), the silicon nitride on the porous filter () dissolves into the etchant (). In the tank (), the silicon nitride dissolved in the etchant () significantly suppresses the etch of silicon dioxide on the semiconductor wafer (), thereby enhancing the etch selectivity of the process. Monitoring and maintaining the concentration of the silicon nitride in the etchant () stabilizes the etch selectivity of the process.

Etch apparatus

In a process using a hot phosphoric acid etchant ( ) to etch silicon nitride on a semiconductor wafer ( ) submerged in a tank ( ) of the etchant ( ), a recirculating path is established for the etchant ( ). A porous filter ( ) is coated with silicon nitride and installed in the recirculating path. As the etchant ( ) in the recirculating path flows through the porous filter ( ), the silicon nitride on the porous filter ( ) dissolves into the etchant ( ). In the tank ( ), the silicon nitride dissolved in the etchant ( ) significantly suppresses the etch of silicon dioxide on the semiconductor wafer ( ), thereby enhancing the etch selectivity of the process. Monitoring and maintaining the concentration of the silicon nitride in the etchant ( ) stabilizes the etch selectivity of the process.

Etch process and apparatus therefor

The present invention is intended for use on BiCMOS technology where the BJTs are formed after the FETs. A thin FET protection layer is deposited on the raised and recessed regions of the semiconductor substrate A selectively removable filler layer is then deposited on the FET protection layer with a thickness to over-fill the recessed regions of the gates of the FETs. The selectively removable filler layer is then planarized until the FET protection layer on top of the gates is exposed. The recessed regions between the gates are left substantially filled with selectively removable filler layer The selectively removable filler layer in the region where the BJT is formed is patterned and an opening is made to allow for the depositing of layers of different materials used in the construction of the BJT. The layer of different materials are processed by methods known in the art to form polysilicon emitter of the BJT. Due to selectively removable filler layer creating a substantially planar surface in the recessed regions of the FETs, little to none of the layers of different materials that are used in the construction of the BJT are deposited within the recessed regions Thus, removal of the layers of different materials ( &prime;), from the FET region is simplified. After removal of the layers of different materials ( &prime;), from the FET region, the selectively removable filler layer is removed selectively to the FET protection layer The FET protection layer is then removed. The recessed regions between the gates of the FETs are free from residual films.

Selectively removable filler layer for BiCMOS process

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Milton, VT, United States of America

Gary L Milo