Intel Corporation

Other

Gary L McAlpine

David B Minturn

Manoj Wadekar

Tanmay Gupta

Gary A Solomon

Edward Butler

Joseph A Schaefer

Greg J Regnier

Oleg Awsienko

David Stewart Dunning

Hemal Vinodchandra Shah

Dave B Minturn

Annie Foong

Donald F Cameron

Vikram A Saletore

Gregory J Regnier

A node uses a two dimensional array of transmit queues to store frames to be transmitted from the node to another node. The size of the array is governed by the number of directions to which the other node may forward frames once received from the node, and the number of priorities that may be associated with the frames. The transmit queues are distinguished from each other based on direction and priority. A transmitter transmits frames dequeued from the transmit queues to the other node. Control logic that controls the transmit queues receives an indication from the other node whether the other node is experiencing traffic congestion in any of the directions and the priority of frames at or below which the control logic is to control the dequeuing of frames from transmit queues corresponding to the directions in which the other node is experiencing traffic congestion.

Directional and priority based flow control mechanism between nodes

A multiple-domain processing system includes a multi-dimensional switching fabric to provide intra-domain and inter-domain communication within the system.

Multiple-domain processing system using hierarchically orthogonal switching fabric

A source node receives related frames of data to be transmitted from the source node to a destination node and places the frames in a queue. The queue is associated with a communication path over which the related frames are to be transmitted to the destination node. An interface that couples the source node to the communication path receives an indication directed to the source node of traffic congestion in the communication path. In response, the source node controls the rate at which the related frames of data are transferred from the queue to a transmit buffer accessible to the interface, in order to relieve the traffic congestion in the communication path.

Congestion control in a network

An apparatus and a system may include an adaptation module, a plurality of Direct Transport Interfaces (DTIs), a DTI accelerator, and a Transport Control Protocol/Internet Protocol (TCP/IP) accelerator. The adaptation module may provide a translated sockets call from an application program to one of the DTIs, where an included set of memory structures may couple the translated sockets call to the DTI accelerator, which may in turn couple the set of memory structures to the TCP/IP accelerator. An article may include data causing a machine to perform a method including: receiving an application program sockets call at the adaptation module, deriving a translated sockets call from the application program sockets call, receiving the translated sockets call at a DTI, coupling the translated sockets call to a DTI accelerator using a set of memory structures in the DTI, and coupling the set of memory structures to a TCP/IP accelerator.

Embedded transport acceleration architecture

A method and apparatus for handling multiple processing streams in parallel on a single thread of a processing device. In one embodiment, a parallel processing agent includes a scheduler that multiplexes a number of processing streams, or pipelines, on a single thread of execution.

Apparatus and method for parallel processing of network data on a single processing thread

An interprocess communication technique transfers a message from a first process' memory (on a first computer system) directly to a second process' memory (on a second computer system). The message is identified by a virtual address and possibly a memory handle. The message is not stored in intermediary memory, such as operating system buffer memory, during the transfer. The communication technique may also provide virtual to physical address translation and memory protection. Memory protection is provided by ensuring that the communicating processes own the memory (the contents of which includes the message) being transferred between them.

Direct message transfer between distributed processes

A digital electronic system architecture having one or more system components and a memory coupled to selected system components, the memory selectively storing and communicating data among the coupled components. The digital electronic system preferably also has a transaction control bus, coupled to each of the selected system components and to the memory, for communicating command and control signals among the components and memory. A memory circuit is provided that has a plurality of ports, each of the ports (i) having an input terminal and an output terminal that transfer data independently of one another, (ii) operating independently of one another and (iii) being coupled respectively to one of the other system components for data communication therewith. A read interface for a memory array is provided that has a queue for receiving data read from a row of the array and a selection circuit for placing in the queue a contiguous block of the read data, the size of the block and its placement being selectable. The read interface preferably comprises a plurality of queues, and the selection circuit preferably is adapted to place independently selectable blocks of the read data in independently selectable positions in selected queues. A write interface for a memory array is also provided that has a queue for receiving data to be written to the array and a selection circuit for placing in the array a contiguous block of received data, the size of the block and its placement being selectable. The write interface preferably comprises a plurality of queues, and the selection circuit preferably is adapted to place independently selectable data received from selected queues in independently selectable positions in the memory array.

High performance digital electronic system architecture and memory

Methods and apparatus process a plurality of interrupt status words from a network interface controller (NIC) to a plurality of processes. A first per-virtual circuit interrupt status word and a second per-virtual circuit interrupt status word can be sent by a per-virtual circuit interrupter having a per-virtual circuit interrupt output. A NIC interrupter can be in communication with the per-virtual circuit interrupt output and have a NIC interrupt output to send a first NIC interrupt status word and a second NIC interrupt status word to a global interrupt queue of a host system. The NIC interrupter can generate an interrupt signal to the host system, and a proxy interrupt handler of the host system can be in communication with the NIC interrupter. The proxy interrupt handler can awaken at least in part in response to the interrupt signal, and read the first NIC interrupt status word and the second NIC interrupt status word from the global interrupt queue, wake the first process and the second process, and send the first NIC interrupt status word to the first process and the second NIC interrupt status word to the second process.

Hierarchical interrupt structure for event notification on multi-virtual

An adaptive rate control scheduler multiplexes virtual circuit data stream elements for transmission onto a network from a network node. The rate control scheduler is an adaptive circuit that utilizes a schedule table (having multiple time windows) and a set of virtual circuit (VC) specific rate control parameters to supply a transmit controller with a stream of tokens (each of which represents an active VC). The order in which tokens are supplied to the transmit controller is based upon their respective time slot locations in the schedule table. Each time a token is processed by the transmit scheduler, a target time for the next processing of the VC represented by the token is calculated, based upon the stored VC-specific parameters. The token is then inserted into the schedule table in the nearest available time slot to the calculated target time. Included in the calculation of the next target time for a particular token is a gain function based upon an accumulated error value for the associated VC. The accumulated error represents error introduced into the VC's data stream by the scheduling process.

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Banks, OR, United States of America

Gary L McAlpine