Intel Corporation

Stexar Corp.

Gary L Brown

Donald D Parker

Darrell D Boggs

Adrian L Carbine

R Guru Prasadh

Michael M Hancock

Rajesh Kumar

Chan W Lee

Ashwani Kumar Gupta

Bradley D Hoyt

Christopher Scott Jones

Gail M Rupnick

Inderpreet S Bhasin

A microprocessor including memory storage into which ISA customer code routines can be stored after having been decoded into their machine-native microinstructions. The customer code store is not subject to eviction and the like, as a cache memory would be. ISA level code can specify a routine for storage into the customer code store, at a time prior to its execution. The customer code store thus serves as a write-once execute-many library of pre-decoded routines which ISA level applications can subsequently use, permitting a system manufacturer to create a highly customized and optimized system.

Microprocessor with customer code store

A system for inserting a supplemental micro-operation sequence into a macroinstruction-generated micro-operation flow provides a versatile, flexible mechanism for early pipeline stages of a microprocessor to pass control signals, data, and other information to later pipeline stages. The mechanism is useful to maintain precise timing of a fault model in pipelined processors. A method includes the step of detecting the occurrence of a predetermined uop-inserting event and, responsive thereto, generating a control signal to a uop insertion unit. Responsive thereto, the uop insertion unit supplies signals to a decoder which, responsive thereto, decodes the signal encoded within the signal to provide the inserted uop sequence, which is inserted in a position within the macroinstruction-generated micro-operation flow predetermined by the uop-inserting event.

System for inserting a supplemental micro-operation flow into a

A circuit and method for supplying and aligning a block of multiple variable length macro instructions to an instruction buffer. Only one cycle is required to align and rotate the block of instruction code. A last byte vector of the instruction code in the instruction buffer is scanned from the last byte in a direction from back to front, thereby saving time. Rotating begins immediately so that a next block of instruction code is available in a next cycle. The block is stored in the instruction buffer after all macroinstructions therein have been steered to the decoder.

Method and apparatus for aligning an instruction boundary in variable

A circuit and method for supplying output length marks indicative of the first bytes and last bytes of instructions in a block of instruction code to an instruction decoder. A block of instruction code is input to an input buffer. A plurality of programmable logic arrays (PLAs) is coupled to receive predetermined sets of bytes from the input buffer and to provide instruction information at an output. The output of the PLAs is coupled to fast carry chain circuitry, which serially processes the information from the PLAs and provides a START mark upon each finding of a first byte of an instruction and an END mark upon each finding of a last byte of an instruction. Length information is provided to wraparound logic for length calculations spanning into the next input buffer of instruction code. A FCC latch latches the output length marks from the fast carry chain circuitry and provides an output to the instruction decoder. If a length-varying prefix and a matching length-varying opcode are both present in an instruction, processing in the fast carry chain circuitry is aborted, and processing in slow carry chain circuitry is started. The slow carry chain circuitry processes information from a subset of the input buffer at a time, and thus requires more than one iteration, with a different set of PLA inputs provided by a multiplexer upon each iteration. A SCC latch latches the output length marks from the slow carry chain circuitry and provides an output to the instruction decoder.

Instruction length decoder for generating output length indicia to

A micro-operation queue for holding a plurality of micro-operations supplied simultaneously by a decoder. A plurality of packing multiplexers are coupled to receive the plurality of micro-operations, and valid bits associated therewith, and to provide packed micro-operation data output in which the valid micro-operations are positioned in adjacent outputs, thereby removing all empty slots. A FIFO queue receives the packed data, in responsive to valid micro-operations, stores the valid micro-operations starting with the next available empty queue location. An embodiment described in which the FIFO queue includes a circular queue with a plurality of entries. In one embodiment, alignment multiplexers for the circular queue are combined with the packing multiplexers, to provide a single-level plurality of packing and aligning multiplexers that has a control system that, responsive to the valid bits of the packed data and the next available pointer of the circular queue, packs, aligns, and stores the micro-operations into the circular queue from where they can be issued.

Packing valid micro operations received from a parallel decoder into

A split queue system for a decoder that supplies one or more micro-operations and data associated with the micro-operations. A main queue is coupled to receive one or more micro-operations from the decoder, and supply it to a next processing stage to provide a process micro-operation. A shadow queue is coupled to receive data associated with the micro-operation, in the same cycle that the micro-operation is supplied to the main queue. A control circuit is coupled to the main queue for issuing micro-operation from the main queue into the next processing stage in a first cycle, and in a second cycle issuing, the micro-operation therefrom. Also in the second cycle, the control circuit issues the data associated with the micro-operation from the shadow queue, so that the data is synchronized with its associated processed micro-operation.

Decoder having a split queue system for processing intstructions in a

A decoder for decoding multiple instructions in parallel, including a full decoder that can decode an instruction into multiple micro-operations, and a partial decoder that can decode a subset of the full instruction set.

Decoder for decoding multiple instructions in parallel

A circuit and method for simultaneously steering multiple aligned macroinstructions from an instruction buffer to a decoder that receives and decodes multiple macroinstructions in parallel. A first macroinstruction is supplied to a first decoder by steering a first predetermined number of bytes following the first buffer byte. A second macroinstruction is supplied by scanning a first opcode byte vector to locate a first opcode byte, and then steering a second predetermined number of bytes beginning at said first opcode to a second decoder. Operations to locate the first byte of each of the macroinstructions and to steer them to the decoders are accomplished in one cycle. If said macroinstruction cannot be decoded by said second decoder, then it is resteered to the first decoder. Steering and resteering operations continue until all complete macroinstructions within the instruction buffer have been accepted by the decoders.

Method for parallel steering of fixed length fields containing a

Decoding circuitry and a method supplying an immediate field that is issued from a decoder. A macroinstruction is supplied to the decoding circuit, which generates a first micro-operation that includes a first aliasing field and a first immediate field. The first aliasing field indicates the source of the micro-operation that will eventually be issued from the decoder. If the source is the first immediate field, then the alias field is further examined to determine the interpretation to be placed upon the data. The data may be interpreted literally, or as an address into a constant ROM, thereby providing an ability to output wide, 32-bit immediate data from a narrower, 9-bit input addresses. Additional sources for immediate data include macro-alias registers, macro-branch information, and micro-branch information.

Decoding circuit and method providing immediate data for a

A state recovery and restart method that simplifies assist handling. The recovery and restart method also handles micro-branch mispredictions. An assist sequence is executed in microcode to assist an error-causing macroinstruction. If data is required from an error-causing macroinstruction, it is fetched, decoded, and macro-alias registers are restored with macro-alias data. To recover the state of the micro-alias registers, micro-alias data from a micro-operation of the flow may be loaded into the micro-alias register. Subsequently, control returns to the Micro-operation Sequence (MS) unit to issue further error correction Control micro-operations (Cuops). In order to simplify restart, the Cuops originating from the error-causing macroinstruction supplied by the translate programmable logic arrays (XLAT PLAs) are loaded into the Cuop registers, with their valid bits unasserted. If microcode requests a restart beginning at one of the Cuops stored in the Cuop register, then the bits for that Cuop and subsequent Cuops are marked valid. Thus, the instruction can be restarted anywhere within the microcode sequence.

Method for state recovery during assist and restart in a decoder having

A decoder that includes a micro-alias register to store information from a micro-operation for use by later micro-operations in the micro-operation flow. The decoder includes one or more XLAT PLAs that produces PLA control micro-operations ('Cuops'), a microcode sequencing unit that produces microcode Cuops, and an aliasing mechanism that extracts fields and stores them in macro-alias registers. A multiplexer is provided to select the appropriate Cuop to be stored in a Cuop register. Multiple Cuops may issue each cycle. A multiplexer is coupled to select one of the Cuops and to store predetermined fields in the micro-alias register for use by subsequent Cuops. Micro-alias data and macro-alias data can be utilized simultaneously with a Cuop to form an Auop.

Decoder having independently loaded micro-alias and macro-alias

A prefix decoder for decoding a plurality of prefixes of a variable length instruction code, in order to supply multiple prefix vectors to a multiple instruction decoder without incurring a one clock penalty. The parallel prefix decoder includes a plurality of prefix decoders, each coupled to receive an instruction byte from an instruction buffer, and in response thereto to supply a prefix vector that includes coded prefix information in a format that is easy to use by subsequent decoder logic. A multiplexer receives the plurality of prefix vectors, and if a steered macroinstruction has a single prefix byte, then a control circuit selects the prefix vector to supply to the macroinstruction decoder. If multiple macroinstructions are steered to multiple macroinstruction decoders, then a prefix vector can be supplied to each decoder.

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Aloha, OR, United States of America

Gary L Brown