Qualcomm Incorporated

Esat Global, Inc.

Gary John Ballantyne

Gurkanwal Singh Sahota

Bo Sun

Jifeng Geng

Daniel Fred Filipovic

Bhushan Shanti Asuri

Jeremy Darren Dunworth

Charles James Persico

Puay Hoe See

Arun Jayaraman

Keith Bargroff

Vladimir Aparin

Chiewcharn Narathong

Aristotele Hadjichristos

Lai Kan Leung

Michael I Parr

Rajagopalan Rangarajan

Jonathan James Klaren

Zae Yong Choi

James Ian Jaffee

Alberto Cicalini

William Ronald Panton

Zixiang Yang

Yi Tang

Masoud Ensafdaran

Puay Hoe Andrew See

Paul L Chan

Walter Scott Charles

Somphou Sithideth

Walter Charles Scott

Charles J c/o Qualcomm Incorporated Persico

Systems are disclosed for a communication system optimized for low data volume communications. In embodiments of the invention, a terminal in the communication system is configured to send and a receiver in the network infrastructure is configured to receive bursts containing pilot waveforms that include time spacing and/or phase changes between short sequences. The time spacing and/or phase changes can be selected to reduce out-of-phase autocorrelation and achieve robust performance.

Low data volume satellite communication system

One feature pertains to a digitally controlled oscillator (DCO) that comprises a variable capacitor and noise reduction circuitry. The variable capacitor has a variable capacitance value that controls an output frequency of the DCO. The variable capacitance value is based on a first bank capacitance value provided by a first capacitor bank, a second bank capacitance value provided by a second capacitor bank, and an auxiliary bank capacitance value provided by an auxiliary capacitor bank. The noise reduction circuitry is adapted to adjust the variable capacitance value by adjusting the auxiliary bank capacitance value while maintaining at least one of the first bank capacitance value and/or the second bank capacitance value substantially unchanged. Prior to adjusting the variable capacitance value, the noise reduction circuitry may determine that a received input DCO control word transitions across a capacitor bank sensitive boundary.

Devices and methods for reducing noise in digitally controlled oscillators

Exemplary embodiments disclosed are directed to power and impedance measurement circuits that may be used to measure power and/or impedance are described. A measurement circuit may include a sensor and a computation unit. The sensor may sense (i) a first voltage signal across a series circuit coupled to a load to obtain a first sensed signal and (ii) a second voltage signal at a designated end of the series circuit to obtain a second sensed signal. The sensor may mix (i) a first version of the first sensed signal with a first version of the second sensed signal to obtain a first sensor output and (ii) a second version of the first sensed signal with a second version of the second sensed signal to obtain a second sensor output. The computation unit may determine the impedance and/or delivered power at the designated end of the series circuit based on the sensor outputs.

Power and impedance measurement circuits for a wireless communication device

A phase locked loop (PLL) device is configurable in an analog phase locked loop and a hybrid analog-digital phase locked loop. In an analog mode, at least a phase detector, an analog loop filter, and a voltage controlled oscillator (VCO), are connected to form an analog loop. In a digital mode, at least the phase detector, the voltage controlled oscillator (VCO), a time to digital converter (TDC), a digital loop filter and a digital to analog converter (DAC) are connected to form the hybrid digital-analog loop.

Configurable digital-analog phase locked loop

A transmitter circuit is described. The transmitter circuit includes a first local oscillator that generates a first frequency equal to a duplex frequency. The transmitter circuit also includes a second local oscillator that generates a second frequency equal to a receive frequency. The transmitter circuit further includes a first mixer that combines the first frequency with a first input signal. The transmitter circuit also includes a first feedback loop. The first feedback loop includes a second mixer that combines the second frequency with a transmit signal and a first filter and a first adder that combines an output of the first mixer with an output of the first filter. The transmitter circuit also includes a third local oscillator that generates a third frequency equal to the receive frequency. The transmitter circuit further includes a third mixer that combines the third frequency with an output of the first adder.

Dual-loop transmit noise cancellation

Techniques for performing analog calibration of a receiver to optimize a second-order input intercept point (IIP2). In an aspect, a signal generator modeling an interferer is coupled to an adjustable input of a receiver, e.g., a gate bias voltage of a mixer. For example, the signal generator output may be a single-tone on-off keying (OOK) modulated signal. The mixer mixes the signal down to baseband, wherein an analog correlator correlates the down-converted signal with the known sequence of bits used to perform the OOK modulation. The analog correlation output is then provided to drive the bias voltage in the mixer, e.g., one or more gate voltages of transistors in the differential mixer, to optimize the overall receiver IIP2. Further aspects of the disclosure provide for calibrating receivers having multiple LNA's, and also dual or diversity receivers having multiple receive paths.

Receiver IIP2 analog calibration

A phase locked loop (PLL) device includes a digital differentiator configured to differentiate a digital loop signal to at least partially compensate for the integration of an analog current signal by an analog integrator. A digital to analog converter (DAC) includes a current source output stage that generates the analog current signal based on an digital input signal. The analog integrator integrates the analog current signal to generate a voltage control signal for controlling a voltage controlled oscillator (VCO).

Phase locked loop with digital compensation for analog integration

A Digital Phase-Locked Loop (DPLL) involves a Time-to-Digital Converter (TDC) that receives a Digitally Controlled Oscillator (DCO) output signal and a reference clock and outputs a first stream of digital values. The TDC is clocked at a high rate. Downsampling circuitry converts the first stream into a second stream. The second stream is supplied to a phase detecting summer of the DPLL such that a control portion of the DPLL can switch at a lower rate to reduce power consumption. The DPLL is therefore referred to as a multi-rate DPLL. A third stream of digital tuning words output by the control portion is upsampled before being supplied to the DCO so that the DCO can be clocked at the higher rate. In a receiver application, no upsampling is performed and the DCO is clocked at the lower rate.

Multi-rate digital phase locked loop

A digitally-controlled oscillator (DCO) of a PLL is dithered such that a DCO_OUT signal has a frequency that changes at dithered intervals. In one example, the DCO receives an undithered stream of incoming digital tuning words, and receives a dithered reference clock signal REFD, and outputs the DCO_OUT signal such that its frequency changes occur at dithered intervals. Where the PLL is employed in the local oscillator of a cellular telephone transmitter, the novel dithering of the DCO spreads digital image noise out in frequency such that less digital image noise is present at a particular frequency offset from the main local oscillator frequency. Spreading digital image noise out in frequency allows a noise specification to be met without having to increase the frequency of the PLL reference clock. By avoiding increasing the frequency of the reference clock to meet the noise specification, increases in power consumption are avoided.

Dithering a digitally-controlled oscillator output in a phase-locked loop

Techniques for cancelling a disturbance signal from a PLL output signal. In an aspect, a cancellation signal is combined with the signal input to a VCO or DCO in the PLL. In a further aspect, the appropriate cancellation signal is derived by analyzing one or more signals within the PLL. The signals within the PLL may be correlated against one or more disturbance signal templates, such as a sinusoid having a known frequency, to derive one or more correlation coefficients. The coefficients may be applied to weight one or more disturbance synthesis functions to generate the cancellation signal. Further aspects provide for joint analysis, synthesis, and cancellation of signals having unknown frequency from the PLL output.

PLL disturbance cancellation

A digital phase-locked loop (DPLL) supporting two-point modulation is described. In one design, the DPLL includes a phase-to-digital converter and a loop filter operating in a loop, a first processing unit for a lowpass modulation path, and a second processing unit for a highpass modulation path. The first processing unit receives an input modulating signal and provides a first modulating signal to a first point inside the loop after the phase-to-digital converter and prior to the loop filter. The second processing unit receives the input modulating signal and provides a second modulating signal to a second point inside the loop after the loop filter. The first processing unit may include an accumulator that accumulates the input modulating signal to convert frequency to phase. The second processing unit may include a scaling unit that scales the input modulating signal with a variable gain.

Digital phase-locked loop with two-point modulation using an accumulator and a phase-to-digital converter

An apparatus comprising a programmable frequency device adapted to generate a reference clock selected from a set of distinct frequency clocks, wherein the programmable frequency device is further adapted to maintain the same temporal relationship of the triggering edges of the reference clock when switching between the distinct frequency clocks. The apparatus further comprises a phase locked loop (PLL), such as a digital PLL (DPLL), that uses the selected reference clock to establish a predetermined phase relationship between an input signal and an output signal. By maintaining substantially the same temporal relationship of the reference clock when switching between distinct frequency clocks, the continual and effective operation of the phase locked loop (PLL) is not significantly disturbed while changing the reference clock. This may be used to control the power consumption of the apparatus.

System and method of controlling power consumption in a digital phase locked loop (DPLL)

In general, the disclosure is directed to techniques for combining a high performance receiver and a low power receiver within a wireless communication device (WCD) to reduce power consumption. Upon receiving a signal from a base station, a controller within the WCD detects one or more channel conditions of a radio frequency (RF) environment between the base station and the WCD. The controller selects a high performance receiver to process the received signal when the RF environment is unfavorable and selects a low power receiver to process the received signal when the RF environment is favorable. In this manner, the WCD implements an adaptive receiver that adapts its receiver structure according to RF channel conditions.

Adaptive receiver for wireless communication device

Transmitters supporting multiple modulation modes and/or multiple frequency bands are described. A transmitter may perform large signal polar modulation, small signal polar modulation, and/or quadrature modulation, which may support different modulation schemes and systems. Circuit blocks may be shared by the different modulation modes to reduce cost and power. For example, a single modulator and a single power amplifier may be used for small signal polar modulation and quadrature modulation. The transmitter may apply pre-distortion to improve performance, to allow a power amplifier to support multiple frequency bands, to allow the power amplifier to operate at higher output power levels, etc. Envelope and phase distortions due to non-linearity of the power amplifier may be characterized for different input levels and different bands and stored at the transmitter. Thereafter, envelope and phase signals may be pre-distorted based on the stored characterizations to compensate for non-linearity of the power amplifier.

Multi-mode and multi-band transmitters for wireless communication

Techniques for dithering quantization thresholds of time-to-digital converters (TDC's) in all-digital phase-locked loops (ADPLL's) are disclosed. In an embodiment, the delay introduced by an individual buffer in a TDC delay line may be dithered. In another embodiment, the delay associated with the TDC delay line may be extended by a fixed amount to accommodate dithering of the zero-delay threshold.

Growing community of inventors

Christchurch, New Zealand

Gary John Ballantyne