Kioxia Corporation

International Business Machines Corporation

Toshiba Memory Corporation

Ocz Storage Solutions Inc.

Gary James Calder

Franz Michael Schuette

Yaron Klein

Philip Rose

Benjamin James Kerr

John Brian Pickering

Neil Buxton

Gavin David Beardall

Julien Margetts

Nigel David Horspool

Robert James Mann

George Murdoch Clelland

Stephen Jeffrey Smith

Allon Leon Cohen

Anthony Timothy Farrell

Paul Reilly

Various implementations described herein relate to systems and methods for protecting data stored on a Solid State Drive (SSD) against malware, including determining, by a controller of the SSD, a typical traffic profile, receiving, by the controller, commands from a host, and determining, by the controller, that the commands are likely caused by malware by determining that the commands deviate from the typical traffic profile. In response to determining the commands are likely caused by the malware, the controller performs a malware response action.

Systems and methods for protecting SSDs against threats

Various implementations described herein relate to systems and methods for a solid state drive (SSD) that includes requesting power credits while performing a program or erase operation for a flash memory of the SSD. In response to determining that the requested power credits are rejected, the program or erase operation is suspended and its power credits are released. A read operation may then be performed in response to suspending the program or erase operation and releasing its power credits.

Systems and methods for scheduling flash operations

A memory system for storing and retrieving data may include a controller, a first switch, a second switch connected to the first switch via an interconnecting bus, and a plurality of memory devices. The controller may have a first serial interface. The first switch may have one or more serial interfaces and one or more memory ports. The first serial interface of the controller may be communicatively connected to a first serial interface of the one or more serial interfaces of the first switch via a first serial bus. Each of the one or more memory ports of the first switch may be communicatively connected to a subset of the plurality of memory devices via a memory bus. The first switch may transfer data between the controller and the subsets of the plurality of memory devices via the one or more memory ports.

System and method for serial interface memory using switched architecture

The current consumed by flash memory devices on the channels of a solid-state drive (SSD) device will be in the form of a time varying waveform, characterized mainly by the types of commands being processed, and are often in the form of periods of constant levels interspersed with very short high current peaks or spikes. When multiple commands are being processed, significant high current peak demands and current surges can occur. The invention described herein is a device and method for scheduling commands to be processed in order to reduce the size of peak current demands and current surges. According to one embodiment of the invention, the device and method for scheduling a command uses look-up tables to determine the time to initiate the processing of the command by the flash memory devices.

Device and method for scheduling commands in a solid state drive to reduce peak power consumption levels

A host server computer system that includes a hypervisor within a virtual space architecture running at least one virtualization, acceleration and management server and at least one virtual machine, at least one virtual disk that is read from and written to by the virtual machine, a cache agent residing in the virtual machine, wherein the cache agent intercepts read or write commands made by the virtual machine to the virtual disk, and a solid state drive. The solid state drive includes a non-volatile memory storage device, a cache device and a memory device driver providing a cache primitives application programming interface to the cache agent and a control interface to the virtualization, acceleration and management server.

Methods and apparatus for providing acceleration of virtual machines in virtual environments

Architectures and methods for performing big data analytics by providing an integrated storage/processing system containing non-volatile memory devices that form a large, non-volatile memory array and a graphics processing unit (GPU) configured for general purpose (GPGPU) computing. The non-volatile memory array is directly functionally coupled (local) with the GPU and optionally mounted on the same board (on-board) as the GPU.

Integrated storage/processing devices, systems and methods for performing big data analytics

Speech encoding in a client server system such as a laptop, personal data assistant or mobile phone communicating with an interactive voice response telephony application. A method of communication with a speech enabled remote telephony device such as a mobile phone is described comprising the following steps. Receiving user speech input into the mobile phone as part of a dialogue with an interactive voice response telephony application. Performing speech recognition to convert the speech into text and converting the text into tones such as DTMF tones. Transmitting the DTMF tones over the voice channel to an interactive voice response (IVR) telephony application an allowed response feature converts the users response to a known valid response of the IVR application. A language conversion feature allows a person in one language to speak in that language to an IVR application operating in a different language.

Speech encoding in a client server system

A coordinate processor for a computer system having an absolute position pointing device (10) such as a touch sensitive display screen comprises stimulus detection means (200) for detecting a tactile stimulus of an absolute position pointing device (10) and directed to a point within a data display area (610) of a computer system. The processor further comprises coordinate locking means (210-320) for locking a current cursor position to the point within the display area corresponding to the tactile stimulus in response to said stimulus exceeding a predetermined threshold value. The processor permits the computer system to distinguish a stimulus of the pointing device (10) for repositioning the cursor within the data display area (610) from a stimulus of the pointing device (10) for issuing a button click command to the computer system. The processor may be embodied in an electronic logic circuit within a pointing device adapter portion of the computer system. Equally, the coordinate processor may be in the form of a central processing unit operating under the control of a computer program.

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Eastleigh, United Kingdom

Gary James Calder