Intel Corporation

Ati Technologies Inc.

Gary J Lavelle

Sridhar Lakshmanamurthy

Blaise B Fanning

Mikal Hunsaker

Michael T Klinglesmith

Robert P Adler

Joseph Murray

Mohan Nair

Rohit R Verma

Louis A Lippincott

Kevin Harney

Richard J Selvaggi

James A Coleman

Atul Kwatra

Joshua Ruggiero

Karthik Vaithianathan

Dinesh G Rao

Mikal C Hunsaker

Jack Tseng

James G Maino

Stephen C Dilliplane

Dharmin Y Parikh

Mohan K Nair

In one embodiment, the present invention includes a method for receiving a request in a router from a first endpoint coupled to the router, where the request is for an aggregated completion. In turn, the router can forward the request to multiple target agents, receive a response from each of the target agents, and consolidate the responses into an aggregated completion. Then, the router can send the aggregated completion to the first endpoint. Other embodiments are described and claimed.

Systems and an apparatus with a sideband interface interconnecting agents with at least one router

Use of hybrid error correcting code (ECC) techniques. A memory access request having an associated address is received. A memory controller determines whether the address corresponds to a first region of a memory for which ECC techniques are applied or a second region of the memory for which ECC techniques are not applied. The memory access is processed utilizing ECC techniques if the address corresponds to the first region of the memory, a transaction indicator and an execution unit indicator, and processed without utilizing the ECC techniques if the address corresponds to the second region of the memory.

Memories utilizing hybrid error correcting code techniques

Aggregating completion messages in a sideband interface

In some embodiments a memory controller is disclosed that includes at least one command/address input buffer to receive commands and addresses. The addresses specify a memory bank and a location within the memory bank. An arbiter, coupled to the at least one command/address input buffer, merges commands and addresses from the at least one command/address input buffer and sorts the commands and addresses based on the addresses specified. A plurality of bank buffers, coupled to the arbiter and associated with memory banks, receive commands and addresses for their associated memory banks. A scheduler, coupled to the plurality of bank buffers, groups commands and addresses based on an examination of at least one command and address from the bank buffers. Other embodiments are otherwise disclosed herein.

Memory controller with bank sorting and scheduling

A display list contains a plurality of entries which each point to a block of data to be displayed on a display screen. An attribute field associated with each entry defines the type of data in the block, so that the data may be properly processed and converted to a displayable image. The display list allows for multiple windows of different data types to be quickly processed and simultaneously displayed on the display screen.

Method and apparatus for displaying multiple windows on a display monitor

A method and apparatus for translating a first address in a first address space, such as a processor address space, to a second address in a second address space, such as system address space, and for accessing a service routine in response to a page fault, are described. In one embodiment, the apparatus for translating comprises a processor; a page table having a translation mask register, a comparison value register, and a replacement value register; and a comparator coupled to the comparison value register and to the replacement value register. A programmable mask within the translation mask register is employed to partition a virtual address. A first subaddress comprises a subset of the bits of the first address and a second subaddress comprises remaining bits of the first address. The first subaddress is masked with a programmable mask value in the translation mask register and is compared by the comparator with successive values in the comparison value register until a match comparison value is found. If a match comparison value is found, a programmable replacement value in the replacement value register corresponding to the match comparison value is concatenated with the second subaddress to provide the second address. If a match comparison value is not found, a fault interrupt is generated to interrupt the translation and the processor accesses a service routine in accordance with the fault interrupt.

Method and apparatus for translating addresses using mask and

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Newtown, PA, United States of America

Gary J Lavelle