Honeywell Information Systems Inc.

Honeywell Bull, Inc.

Gary J Goss

Thomas O Holtey

Kin C Yu

Thomas L Murray, Jr

Robert G Moles

Randall D Hinrichs

Kenneth E Bruce

James W Stonier

Thomas F Joyce

Richard P Kelly

Robert C Miller

Thomas S Hirsch

Allen C Hirtle

James C Siwik

Angelo D Kachemov

Robert M Daly

John E Mekota, Jr

A computer system includes a first processor with main memory, an input/output processor with associated memory and an archival memory. Prior to reloading a new operating system from archival memory into the main memory, information such as timer information is stored in the input/output memory. The input/output memory continues to update the timer information until the second operating system is bootstrap loaded into the main memory. The timer and other information may then be returned to the first processor and main memory for use by the second operating system.

Facility for passing data used by one operating system to a replacement

A display subsystem having a graphics capability includes a bit map memory for storing bits, each bit representing a displayed pixel. A read only memory stores words, each word representative of a pixel of a selected pattern which is used to fill out an area of the display thereby clearly identifying adjacent areas of the display to the operator. The selected patterns are displayed in a REPLACE, an OR or an EXCLUSIVE OR mode of operation.

Pattern generation for a graphics display

A Loadable Character Generator whose operation can be changed to suit various needs, such as foreign language requirements, without hardware change and with minimum hardware. The character generator translates the character code of a character to be displayed to the dot pattern for that particular character, utilizing a minimum of hardware. The loadable character generator of the invention replaces the ROM/PROM by a RAM utilizing 2K and 8 RAM memories, a 4K by 8 memory, 4 MUX chips, and a Motorola 6845 CRT Controller with various registers and is loaded through the attribute buffer.

Variable loadable character generator

A color display graphics system includes three bit map memories for storing bits representing red, green and blue colors respectively. Combinations of bits from the same address locations of each bit map memory display a pixel which could be any one of eight colors: black, blue, green, cyan, red, magenta, yellow or white. A read only memory (ROM) stores patterns made up of sixteen bits in a four-by-four matrix for each of the red, green and blue colors. The 16-bit matrices are stored in their respective bit map memories for subsequent color display. Combinations of matrices may be used to show shades of the above eight colors and the mixing of any of those shades.

Multiple color generation on a display

A data processing system includes a central processing unit (CPU), an input/output microprocessor, a main memory and a number of mass storage controllers. A block of information is transferred between one of the mass storage controllers and main memory during data multiplex control (DMC) cycles. The CPU includes registers which store the address of main memory into which the next data byte is written or read from and the range indicating the number of data bytes remaining to be transferred. Prior to a DMC cycle the CPU stores address and range information in a mailbox location in an I/O RAM and the I/O microprocessor transfers that information to channel table locations in the I/O RAM. For a DMC operation, the I/O microprocessor transfers the address and range information to the mailbox location and transfers the mass storage information to the mass storage controller. It signals a CPU interrupt and issues a read or write order to the mass storage controller. The CPU then retrieves the address and range information from the mailbox location and initiates a DMC cycle.

Data multiplex control facility

A microprogrammed data processing system includes a central processing unit (CPU), a main memory and a number of mass storage controllers. A block of information is transferred between main memory and one of the mass storage controllers during data multiplex control (DMC) cycles. The main memory stores 2 data bytes in each word location. An input/output RAM stores channel number signals for identifying mass storage controllers. An I/O microprocessor addresses the I/O RAM to read the channel number signals onto the system bus, and a mass storage controller coupled to the system bus responds to the channel number signals to generate a read/write signal. The system responds to a request signal, the read/write signal and a signal indicative of a left or right bit of an addressed location in main memory to generate a plurality of data request signals. A read only memory is addressed in response to the data request signals to read out a plurality of microprograms for processing the data.

Speeding up the response time of the direct multiplex control transfer

An apparatus for decoding data wherein only binary ZEROs are received as electronic pulses, each pulse alternating in opposite directions and wherein binary ONEs require no pulse. The apparatus includes logic for receiving the negative and positive binary ZERO pulses, retiming the pulses and generating a positive pulse for each binary ZERO pulse. The positive pulse is retimed to a pair of complementary pulses and applied to a receiving device, typically a universal synchronous/asynchronous receiver transmitter (USART).

Digital decode logic for converting successive binary zero pulses having

An apparatus for decoding and synchronizing data wherein only logic ZERO data bits are received as electronic pulses, each pulse alternating in opposite directions and wherein logic ONE data bits are received as no pulse. The synchronization logic includes a counter which is delayed a count of binary ONE if the logic ZERO data bit is received late, and the counter is advanced a count of binary ONE if the logic ZERO data bit is received early.

Digital apparatus for synchronizing a stream of data bits to an internal

An apparatus for encoding data for serial transmission wherein only logic ZEROs are transmitted as electronic pulses, each pulse alternating in opposite direction and wherein logic ONEs require no pulse.

Digital serial interface with encode logic for transmission

In a data processing system having a plurality of units coupled for the transfer of information therebetween over a common electrical bus or for transferring information via a communication channel to other data processing systems during asynchronously generated information bus transfer cycles, an apparatus exists for reformatting data for transfer over the common electrical bus or via the communication channel. The apparatus is comprised of an eight-way multiplexer responsive to control bits for selecting one of eight different formats during write or read operations to or from a memory. Additionally, during read operations, the apparatus transfers a return address from a unit requesting information to the address bus so that data read from memory may be transferred to the requesting device. The formatting control bit is similarly reformatted from the data bus to the address bus bit.

Automatic data steering and data formatting mechanism

A data processing system includes a communication subsystem having an I/O microprocessor for communicating with a central processing unit and a main memory; and a line microprocessor for communicating with a number of devices. The I/O microprocessor and the line microprocessor communicate with each other through mailboxes stored in a shared memory. The line microprocessor interrupts the I/O microprocessor to process data bytes being transferred between main memory and a device requesting service when the line microprocessor has responded to the requesting device and loaded the mailbox.

Communication multiplexer having dual microprocessors

A data processing system includes a central processing unit, a main memory, and a communication subsystem servicing a number of communication lines. The communication subsystem includes a free running timer, a line microprocessor for communicating with the communication lines and a shared memory, and an I/O microprocessor for communicating with the shared memory and the central processing unit and main memory. The line microprocessor, desiring to communicate with a specified communication line after a predetermined time delay, loads a first mailbox in shared memory with a binary number indicative of the predetermined time delay. The I/O microprocessor adds the output of the free running timer to the binary number, stores the result in a location in a random access memory, and periodically compares the result against the free running timer output. The I/O microprocessor loads a second mailbox with a control character when the results of the comparison indicate that the predetermined time delay is accomplished. The line microprocessor responds to the information in the second mailbox to communicate with the specified communication line.

Communication multiplexer sharing a free running timer among multiple

A data processing system includes a central processing subsystem, a main memory subsystem, and a number of peripheral subsystems including a communication subsystem all coupled in common to a system bus. Subsystems communicate with each other during asynchronously generated information bus transfer cycles. Each one of the subsystems receives information by providing any one of three signal responses including a positive acknowledge signal indicating an immediate response, a negative acknowledge signal indicating that the unit will most likely be busy for an extended period of time, and a quasi-negative response indicating that the unit will probably be ready during the next asynchronously generated bus transfer cycle. In order to expediate the response in the case of the transfer over the system bus of an input/output order from the central processing subsystem to the communication subsystem, apparatus in the communication system stores a positive acknowledge or a negative acknowledge signal for each communication channel. The signal is set to indicate a negative acknowledge when the previous input/output order filled the last communication control block. The signal is set to indicate a positive acknowledge when the previous input/output order emptied the communication control block.

Communication multiplexer using a random access memory for storing an

A data processing system includes a number of input/output devices coupled to a communication multiplexer which polls the devices in a predetermined order. Apparatus in the communication controller rearranges the polling order to provide highest priority to an input/output device in a receive mode that is currently operative and to give lowest priority to an input/output device in a transmit mode that has just completed its operation.

Communication multiplexer having a variable priority scheme using a read

A communication multiplexer stores the receive and transmit channel numbers of input/output devices coupled to the multiplexer by communication lines in a first-in-first out (FIFO) memory. The input/output devices are polled by sending the channel numbers from the FIFO to the input/output devices. An input/output device requesting service responds to its channel number. The remaining channel numbers in the FIFO are recirculated to give the receive channel numbers priority over the transmit channel numbers. This gives high priority to a most recently used receive channel operative in a burst mode and equal priority to all transmit channels.

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Acton, MA, United States of America

Gary J Goss