Qualcomm Incorporated

Gary J Ballantyne

Bhushan Shanti Asuri

Jeremy Darren Dunworth

Jifeng Geng

Gurkanwal Singh Sahota

Bo Sun

Techniques for decimating a first periodic signal to generate a second periodic signal. In an exemplary embodiment, the first periodic signal is divided by a configurable integer ratio divider, and the output of the divider is delayed by a configurable fractional delay. The configurable fractional delay may be noise-shaped using, e.g., sigma-delta modulation techniques to spread the quantization noise of the fractional delay over a wide bandwidth. In an exemplary embodiment, the first and second periodic signals may be used to generate the transmit (TX) and receive (RX) local oscillator (LO) signals for a communications transceiver from a single phase-locked loop (PLL) output.

Signal decimation techniques

A method of performing modulation of a data signal at a phase-locked loop (PLL) includes generating, at an upper frequency port of the PLL, a digital loop signal based at least in part on the data signal. The method further includes differentiating the digital loop signal to generate a digital input signal and converting the digital input signal to an analog current signal. A first feedback signal is generated based on the analog current signal. The method further includes generating, at a lower frequency port of the PLL, a second feedback signal based on the first feedback signal and further based on the data signal. According to further embodiments, apparatuses and a computer-readable medium are disclosed.

Phase locked loop with digital compensation for analog integration

A phase locked loop (PLL) device is configurable in an analog phase locked loop and a hybrid analog-digital phase locked loop. In an analog mode, at least a phase detector, an analog loop filter, and a voltage controlled oscillator (VCO), are connected to form an analog loop. In a digital mode, at least the phase detector, the voltage controlled oscillator (VCO), a time to digital converter (TDC), a digital loop filter and a digital to analog converter (DAC) are connected to form the hybrid digital-analog loop.

Configurable digital-analog phase locked loop

A power amplifier circuit arrangement particularly useful for portable phones used in wireless systems. A power amplifier stage can be partially or completely bypassed so that multi-stage amplifiers can be built that allow wide dynamic range of power amplification to be obtained efficiently. A switch at the input of an amplifier stage couples an input signal either to an amplifier or to a bypass path. The output of the amplifier is coupled to a first impedance-transforming network. The bypass path includes a second impedance-transforming network. A third impedance transforming network couples the outputs of the first and second impedance transforming networks. The impedance transforming networks are constructed and arranged so that input and output signals see the correct load regardless of whether the amplifier is used or bypassed. Using the principles of this invention, multi-stage amplifiers can be constructed including input and bypass attenuators to achieve a wide range of gain levels.

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San Diego, CA, United States of America

Gary J Ballantyne