Semiconductor Components Industries, LLC

Motorola Corporation

Hvvi Seminconductors, Inc.

Gary Horst Loechelt

Gordon M Grivna

Peter J Zdebel

Prasad Venkatraman

John Michael Parsey, Jr

Robert Bruce Davies

Dean E Probst

Balaji Padmanabhan

Mohammed Tanvir Quddus

Thierry Coffi Herve Yao

Moshe Agam

Julio C Costa

Muh-Ling Ger

Tirthajyoti Sarkar

Wonhwa Lee

Misbahul Azam

Ladislav Seliga

Jaroslav Pjencák

David H Lutz

Patrice M Parris

Peter Moens

Joseph Andrew Yedinak

Zia Hossain

James P Morgan

Yenting Wen

Andreas A Wild

Piet Vanmeerbeek

Xiaoli Wu

Juan Buxo

Michael A Stapleton

Thomas E Zirkle

E James Prendergast

Kisun Lee

Carroll Casteel

John M Parsey

Marco Fuhrmann

Devices and methods are disclosed for facilitating faster switching of silicon-based and silicon carbide-based power transistors suitable for use in electric vehicles. The disclosed techniques can minimize the impact on turn-on and turn-off losses, while reducing gate voltage and drain voltage spikes during device switching. A fast/slow cell design incorporating shielded gate MOSFETs controls gate-to-drain capacitance and gate resistances to optimize suppression of voltage overshoot.

Method for suppressing voltage overshoots

In a general aspect, a semiconductor device can include a semiconductor region, an active region disposed in the semiconductor region, a termination region disposed on the semiconductor region and adjacent to the active region, and a resistor disposed in the termination region. The resistor can include a trench, a conductive material disposed in the trench, and a first cavity separating the trench from the semiconductor region. A portion of the first cavity can be disposed between a bottom of the trench and the semiconductor region. The resistor can further include a second cavity separating the trench from the semiconductor region.

Dielectric lattice with passive component circuits

In a general aspect, a semiconductor device can include a semiconductor region, an active region disposed in the semiconductor region, and a termination region disposed on the semiconductor region and adjacent to the active region. The termination region can include a trench having a conductive material disposed therein. The termination region can further include a first cavity separating the trench from the semiconductor region. A portion of the first cavity can be disposed between a bottom of the trench and the semiconductor region. The termination region can also include a second cavity separating the trench from the semiconductor region.

Dielectric lattice with capacitor and shield structures

A method of forming a power semiconductor device includes providing an epi layer over a substrate; forming a well at an upper portion of the epi layer; forming a pillar below the well and spaced apart from the well to define a Schottky contact region; etching a trench into the epi layer, the trench having a sidewall and a base, a portion of the sidewall of the trench corresponding to the Schottky contact region; forming a metal contact layer over the sidewall and the base of the trench, the metal contact layer forming a Schottky interface with the epi layer at the Schottky contact region; and forming a gate electrode and first and second electrodes.

Power device having super junction and Schottky diode

A circuit and physical structure can help to counteract non-linear Cassociated with power transistors that operate at higher switching speeds and lower R. In an embodiment, a component with a pn junction can be coupled to an n-channel IGFET. The component can include a p-channel IGFET, a pnp bipolar transistor, or both. A gate/capacitor electrode can be within a trench that is adjacent to the active regions of the component and n-channel IGFET, where the active regions can be within a semiconductor pillar. The combination of a conductive member and the semiconductor pillar of the component can be a charge storage component. The physical structure may include a compensation region, a barrier doped region, or both. In a particular embodiment, doped surface regions can be coupled to a buried conductive region without the use of a topside interconnect or a deep collector type of structure.

Electronic device including a charge storage component

In a general aspect, a transistor can include a trench disposed in a semiconductor region and a gate electrode disposed in an upper portion of the trench. The gate electrode can include a first and second gate electrode segments. The transistor can also include a shield electrode having a first shield electrode portion disposed in a lower portion of the trench, and a second shield electrode portion orthogonally extending from the first shield electrode portion in the lower portion of the trench to the upper portion of the trench. The first shield electrode portion can be disposed below the first and second gate electrode segments, and the second shield electrode portion can being disposed between the first and second gate electrode segments. The transistor can also include a patterned buried conductor layer. The first and second gate electrode segments can be electrically coupled via the patterned buried conductor layer.

Trench gate transistors with low-resistance shield and gate interconnects

An electronic device can include doped regions and a trench disposed between the doped regions, wherein the trench can include a conductive member. In an embodiment, a parasitic transistor can include doped regions as drain/source regions and the conductive member as a gate electrode. A semiconductor material can lie along a bottom or sidewall of the trench and be a channel region of the parasitic transistor. The voltage on the gate electrode or the dopant concentration can be selected so that the channel region does not reach inversion during the normal operation of the electronic device.

Electronic device including doped regions and a trench between the doped regions

An electronic device can include a semiconductor layer having a primary surface, a drift region adjacent to the primary surface, a drain region adjacent to the drift region and extending deeper into the semiconductor layer as compared to the drift region, a resurf region spaced apart from the primary surface, an insulating layer overlying the drain region, and a contact extending through the insulating layer to the drain region. In an embodiment, the drain region can include a sinker region that allows a bulk breakdown to the resurf region to occur during an overvoltage event where the bulk breakdown occurs outside of the drift region, and in a particular embodiment, away from a shallow trench isolation structure or other sensitive structure.

Electronic device including a drift region

A power semiconductor device includes a semiconductor layer having a first conductivity type. A trench is defined within the semiconductor layer, the trench having an opening, a sidewall and a base. A pillar is provided below the trench and has a second conductivity type that is different than the first conductivity type. A metal layer is provided over the sidewall of the trench, the metal layer contacting the semiconductor layer at the sidewall of the trench to form a Schottky interface of a Schottky diode. A first electrode is provided over a first side of the semiconductor layer. A second electrode is provided over a second side of the semiconductor layer.

Power device having super junction and schottky diode

An electronic device can include a transistor having a drain region, a source region, a dielectric layer, and a gate electrode. The dielectric layer can have a first portion and a second portion, wherein the first portion is relatively thicker and closer to the drain region; the second portion is relatively thinner and closer to the source region. The gate electrode of the transistor can overlie the first and second portions of the dielectric layer. In another aspect, an electronic device can be formed using two different dielectric layers having different thicknesses. A gate electrode within the electronic device can be formed over portions of the two different dielectric layers. The process can eliminate masking and doping steps that may be otherwise used to keep the drain dopant concentration closer to the concentration as originally formed.

Electronic device including a dielectric layer having a non-uniform thickness

An electronic device can include a transistor structure. In an embodiment, the transistor structure can include a channel region and a drift structure including different semiconductor base materials. In another embodiment, the transistor structure can include a source region and a drain structure including a first region, wherein the source region and the first region include different semiconductor base materials and have the same conductivity type. In another aspect, a process of forming an electronic device can include forming a semiconductor layer; forming a body region; patterning the body region and the semiconductor layer to define a trench having a sidewall; forming a first region of a drain structure along the sidewall of the trench, wherein the first region and body region include different semiconductor base materials and different conductivity types.

Electronic device including a transistor structure having different semiconductor base materials

An electronic device can include a termination structure that includes a substrate, a semiconductor layer, and a first trench. The substrate includes a semiconductor material of a first conductivity type. The semiconductor layer has a second conductivity type opposite the first conductivity type and overlies the substrate and has a primary surface. The first trench extends through a majority of a thickness of the semiconductor layer. In an embodiment, a body extension region of the second conductivity type is adjacent to the primary surface and spaced apart from the first trench. In another embodiment, a doped region of the first conductivity type is adjacent to the primary surface and abuts the first trench. In a further embodiment, the termination structure can include a second trench extending through a majority of the thickness of the semiconductor layer and a doped region is spaced apart from the first and second trenches.

Electronic device including a termination structure

A circuit can include a field-effect transistor having a body, a drain, a gate, and a source. In an embodiment, the circuit can further include a bipolar transistor having a base and a collector, wherein the collector of the bipolar transistor is coupled to the body of the field-effect transistor; and the drain of the field-effect transistor is coupled to the base of the bipolar transistor. In another embodiment, the circuit can include a diode having an anode and a cathode, wherein the source of the field-effect transistor is coupled to the anode of the diode, and the gate of the field effect transistor is coupled to the cathode of the diode. In another aspect, an electronic device can include one or more physical structures that correspond to components within the circuits.

Electronic device including a ring suppression structure

Process of forming an electronic device including a drift region, a sinker region and a resurf region

A circuit can include a pair of switching devices that are coupled to an intermediate switching node and another pair of switching devices that are coupled to an output node. The circuit can further include a magnetic element that can help to store energy when the circuit transitions from a low state to a high state and release the energy when the circuit transitions from a high state to a low state. The circuit can include a control device to allow synchronous operation between the different pairs of switching devices. The magnetic element can help to reduce voltage swings at the output switching node. Thus, switching devices within each of the pairs can be optimized to allow for better performance of the circuit.

Circuit including dual power converters and an inductor and a method of using an electronic device including a circuit including dual power converters and an inductor

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Tempe, AZ, United States of America

Gary Horst Loechelt