Dialog Semiconductor (uk) Limited

Dialog Semiconductor Gmbh

Apple Inc.

Silego Technology Inc.

Gary Hague

Ambreesh Bhattad

Frank Kronmueller

Hande Kurnaz

Horst Knoedgen

Julian Tyrrell

Sebastian Loeda

John William Kesterson

Nebojsa Jelaca

David P Tester

Rupert Howes

Edgar Sexauer

Andrew Repton

Jung Woo Choi

Markus Engelhardt

Sander Heuvelmans

Jorg Medwed

The present document relates to differential amplifiers. A differential amplifier may comprise a current source, a first transistor, a second transistor, and a compensation circuit. A reference voltage may be applied to a first terminal of the first transistor, and a second terminal of the first transistor may be coupled to an output of the current source. A feedback voltage may be applied to a first terminal of the second transistor, and a second terminal of the second transistor may be coupled to the output of the current source. The compensation circuit may comprise a capacitive element coupled to the first terminal of the first transistor, and the compensation circuit may be configured to reduce a change of the reference voltage at the first terminal of the first transistor.

Differential amplifier

A conductive liquid path detection circuit for detecting a conductive liquid present in a receptacle connector and/or a mating connector plug is configured for discharging an electron charge from any conductive liquid present on a connector pin in the receptacle connector and/or a mating connector plug. The conductive liquid path detection circuit charges any conductive liquid present on the connector pin with an electron charge. The circuit repeatedly samples and retains the samples of the measurements of a voltage level present at the connector pin. The conductive liquid path detection circuit then analyzes the samples of the measurements to determine a slope of the samples of the measurements of a voltage level over time; and determines when an amplitude of a final measurement of the voltage level is less than a conductive liquid detection threshold level.

Wet contact detection in external accessory connector

A regulator configured to provide at an output node a load current at an output voltage is described. The regulator comprises a pass transistor for providing the load current at the output node. Furthermore, the regulator comprises feedback means for deriving a feedback voltage from the output voltage at the output node. In addition, the regulator comprises a differential amplifier configured to control the pass transistor in dependence of the feedback voltage and in dependence of a reference voltage. The regulator further comprises compensation means configured to determine a sensed current which is indicative of the load current at the output node. Furthermore, the compensation means are configured to adjust an operation point of the regulator in dependence of the sensed current and in dependence of a value of a track impedance of a conductive track which links the output node to a load.

Voltage regulator with impedance compensation

The present document discloses a circuitry for delaying a digital input signal. In particular, the circuitry may comprise a delay cell circuit and a reciprocal current digital-to-analog converter (DAC). The delay cell circuit may be coupled to the reciprocal current DAC. More particularly, the reciprocal current DAC may be configured to output a charge current to the delay cell circuit according to a value of a control input provided to the reciprocal current DAC. The charge current output by the reciprocal current DAC may be inversely proportional to the value of the control input, wherein the delay depends on the charge current.

Linear delay generation circuitry and method

A memory element is provided in which a logical state can be securely stored in all conditions even when input set and reset signals are overlapping. This is achieved through provision of an array of persistence latches with an asynchronous circuit that ensures correct operation. The persistence latches provide a persistent output for each of the first and second edges of each input. The memory element is arranged to receive a plurality of inputs including a first and second input. Each first and second inputs include a digital signal that can transition between a first state via a first edge which triggers transition from the first state to the second state and a second edge which triggers transition from the second state to the first state.

Secure memory element for logical state storage

A driver circuit for generating a sequence of pulses of a drive voltage from a supply voltage is described. The drive voltage is used for operating an electrical actuator, such as an electrical engine or machine. The driver circuit comprises means for providing an amplitude indication of an amplitude of the supply voltage, which is used for generating a first pulse of the sequence of pulses. Furthermore, the driver circuit comprises an integration unit configured to integrate the amplitude indication for a duration of the first pulse, thereby generating an integrated voltage. In addition, the driver circuit comprises a comparator configured to compare the integrated voltage with a reference voltage, thereby generating a comparator signal. Furthermore, the driver circuit comprises a control unit configured to terminate the first pulse in dependence of the comparator signal.

PWM actuator control with pulse regulation

An apparatus and a method for generating a pulse width modulated, PWM, voltage doubler signal is presented The apparatus comprises a voltage source, a capacitor, an output node, a switchable circuit assembly for connecting the voltage source, the capacitor and the output node, and a controller for the switchable circuit assembly which is adapted to be switchable between a first circuit configuration in which the capacitor is connected in parallel to the voltage source so as to be chargeable by the voltage source, and a second circuit configuration in which the capacitor is connected in series between the voltage source and the output node, and wherein the control means is adapted to control the switchable circuit assembly to switch to the first circuit configuration in the first period, and to switch to the second circuit configuration in the second period.

Voltage doubler and voltage doubling method for use in PWM mode

A controller for a driver circuit of a solid state lighting (SSL) device is described. The driver circuit comprises a power converter to transfer energy from AC mains voltage to the SSL device. The controller determines a dim level for the SSL device. The controller also determines a synchronization signal by comparing a voltage derived from the input voltage with a pre-determined threshold. The controller determines a sequence of PWM pulses based on the synchronization signal. The controller operates the power converter in a first operation mode for supplying energy to the SSL device at a first energy level within the sequence of PWM pulses, and operates the power converter in a second operation mode in between the PWM pulses. The second energy level is lower than the first energy level and the first energy level and/or a width of the PWM pulses depend on the dim level.

Accurate mains time-base for LED light driver

A summing-tracking quantizer additively combines multiple feed-forward outputs of cascaded integrator stages of a sigma-delta analog-to-digital converter with a scaled sampled analog signal, and a delayed scaled analog input signal. The summing tracking quantizer compensates for loop delay within a sigma-delta analog-to-digital converter. A loop delay compensation digital-to-analog converter for a sigma-delta analog-to-digital converter is merged with the voltage reference generator within the summing-tracking quantizer. The summing tracking quantizer selects reference voltages from the voltage reference generator based on a previous digital output code. The summing-tracking quantizer has a matrix switch that receives the previous digital output code and selects the reference voltage for applying to comparators for determining a differential quantization code that is additively combined to the previous digital output code to determine the present digital output code.

Compensation of loop-delay quantizer in continuous-time and hybrid sigma-delta analog-to-digital modulators

An audio device () includes a first and second ICs () and () and a substrate (). The first IC includes a sigma-delta, A/D converter () operable to convert an analog signal () into a pulse density modulated signal (). A pulse density width modulator encoder () is operable to encode the PDM signal into a PDWM signal (). The PDWM has short and long pulse widths defining first and second bit levels. The leading edges of each pulse bounds each pulse period. The second IC () includes a means () to receive the PDWM signal, an edge detector () operable to detect the leading pulse edges of the PDWM signal, a time-averaging circuit () operable to calculate each pulse period from the leading pulse edges and to generate a sample pulse () at near the midpoint of each pulse period, and a latch () operable to sample and hold the PDWM signal at the sample pulse to decode a PDM signal (). The substrate is operable to support the first and second ICs and to conduct the PDWM signal between the first and second ICs.

Device and method for the transmission and reception of high fidelity audio using a single wire

An accurate high current mirror circuit produces a mirrored current that matches an input current to produce an accuracy at the output of a subsequent stage of amplification of greater than 0.01%. A plurality of transistor devices are arranged in a symmetrical configuration and divided into two groups. The transistors in each of the two groups are connected in parallel to produce a high mirror current from a high input current. A distribution of a source voltage produces the same source voltage at each of the plurality of transistors. An input current metallization and a mirror current metallization are formed within the symmetrical configuration to have a same value of impedance. A plurality of P-channel transistors within the current mirror circuit control a voltage of a point on the input metallization to be the same as a reference voltage, thus causing the mirror current to be referenced around the reference voltage.

Method for implementation of a low noise, high accuracy current mirror for audio applications

A system and methods to convert a digital bit stream to analog values without previous knowledge of the sample rate of the incoming digital bit stream has been achieved. The system comprises a sample rate measurement device being able to measure the sample rate out of the incoming digital bit stream. Another device is removing all bits, which are not required for the digital to analog conversion from the incoming bit stream. The measured and calculated sample rate is added to the 'cleaned' bit stream and a digital to analog conversion device is performing the conversion using the sample rate which has been added to the bit stream.

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Swindon, United Kingdom

Gary Hague