Celis Semiconductor Corporation

Symetrix Corporation

Other

Matsushita Electronics Corporation

Inmos Limited

Siemens Aktiengesellschaft

Gary F Derbenwick

Narayan Solayappan

Alan D DeVilbiss

David A Kamp

Carlos Alberto Paz De Araujo

Larry D McMillan

Shinichiro Hayashi

Michael C Scott

Michael V Cordoba

Matthew Hanson

William Dennis Ryden

Daryl G Dietrich

James R Adams

George B Coombe

Walter Hartner

Ryan Tasuo Hirose

Vikram Joshi

Alfred P Gnadinger

Gunther Schindler

Carlos Mazure

Troy A Meester

The present invention includes apparatus and a method for reading one or more data states from an integrated circuitry memory cell, including the steps of connecting the memory cell to a bit line which is connected to an amplifier having an offset control which introduces an offset during the sensing portion of a read cycle to identify a data state stored in the memory cell.

Integrated multilevel memory apparatus and method of operating same

An integrated circuit memory contains a memory cell connected to a bit line that does not float during a portion or all of the read sensing part of the read cycle. The memory cell includes a data storage device. The data storage device may be a ferroelectric capacitor, a linear capacitor, a floating gate transistor, a magnetic device, a resistive device or other type of data storage device capable of placing a charge on the bit line corresponding to a specific data state of the memory cell. The bit line and a reference bit line are connected to a differential amplifier and precharged to specified voltages. Preferably, a self-nulling sense amplifier circuit is connected to the bit lines that compensates for sense amplifier offset by applying additional charges on the bit lines. Alternatively, charge sources may be connected to the bit lines to provide additional charges on the bit lines during the read cycle. Memory cells according to this invention can be configured to provide a reference cell for the reference bit line.

Integrated memory device and method of operating same

A rectifier generates a rectified output and a dc power output. The rectifier has an antenna element, a tuning capacitor, a coupling capacitor, first and second rectifying diodes, and a storage capacitor. The antenna element and the tuning capacitor are coupled in parallel and grounded at one terminal. The first rectifying diode is grounded at its anode terminal and the storage capacitor is grounded at one terminal. The coupling capacitor is coupled between the ungrounded terminal of the antenna element and the cathode terminal of the first rectifying diode. The anode terminal of the second rectifying diode is coupled to the cathode terminal of the first rectifying diode. The cathode terminal of the second rectifying diode is coupled to the ungrounded terminal of the storage capacitor. The rectified output is generated between the rectifying diodes. The dc power output is generated between the second rectifying diode and the storage capacitor.

Rectifier utilizing a grounded antenna

An electrical circuit is formed by forming and patterning a conductive layer on a substrate, forming and patterning a conductive layer on another substrate, depositing a dielectric layer on at least a portion of one of conductive layers, mounting an integrated circuit (IC) between the substrates, coupling the IC to the conductive layers, and affixing the substrates together with the conductive layers between the substrates. These are either separate substrates or a unitary substrate. The IC is mounted either to a substrate, a conductive layer, or a dielectric layer. The IC is coupled to the conductive layers either directly or through openings formed in the dielectric layer. An interior conductive layer may be used to couple the IC to the conductive layers.

Method for producing an electrical circuit

A ferroelectric layer within an array of ferroelectric FETs is encapsulated between a bottom barrier dielectric layer and a top barrier dielectric layer extending beyond the ferroelectric layer. The ferroelectric FETs are formed on first conductivity type silicon, each having two second conductivity type silicon regions within the first conductivity type silicon separated by some distance. The two second conductivity type silicon regions forming a source and a drain with a channel region therebetween. A silicon dioxide layer is formed on the channel region, a bottom barrier dielectric layer is formed on the silicon dioxide layer, a ferroelectric layer is formed on the bottom barrier dielectric layer, a top barrier dielectric layer is formed on the ferroelectric layer, and an electrode layer is formed on the ferroelectric layer.

Encapsulated ferroelectric array

A ferroelectric integrated circuit memory device includes: a plurality of memory cells, each including a ferroelectric material, a plurality of conducting lines, each connected to or connectable to a selected one of the memory cells; a drive circuit for applying a predetermined voltage for a predetermined time to a selected one of the conducting lines, the predetermined voltage and time being the normal voltage and time required to perform write or read functions to the memory cell, a function selected from the group of: writing a logic state to the selected memory cell, and reading the selected memory cell; and a mode control circuit responsive to an external signal for adjusting the predetermined voltage or the predetermined time to perform an operation selected from the group consisting of: a partial read of the selected memory cell, and a partial write of the selected memory cell; and applying ferroelectric stress to the memory cell. A known logic state is written to the memory cells, the cells are heated, and then read to provide output data indicative of the likelihood of premature failure for each of the memory cells. Ferroelectric stress is applied to the cells either before or after the cells are written to by repeatedly applying a voltage to the cells corresponding to a logic state opposite that of the written logic state.

Apparatus and method for testing ferroelectric memories

A ferroelectric destructive read-out memory system includes a power source, a memory array including a memory cell, and a logic circuit for applying a signal to the memory array. Whenever a low power condition is detected in said power source, a disturb prevent circuit prevents unintended voltages due to the low power condition from disturbing the memory cell. The disturb prevent circuit also stops the operation of the logic circuit for a time sufficient to permit a rewrite cycle to be completed, thereby preventing loss of the data being rewritten.

Electronic memory with disturb prevention function

A timing circuit produces a clock signal. An address buffer circuit receives and stores a first address in a first latch and a second address in a second latch asynchronously with respect to the clock signal. A memory control circuit associated with an array of memory cells accesses a first memory cell in the array corresponding to the first address in a first clocked access cycle, and accesses a second memory cell in the array corresponding to the second address in a second clocked access cycle. If a further address is asynchronously received before said second access cycle, the further address replaces the second address in the second latch.

Asynchronously addressable clocked memory device and method of operating same

A ferroelectric integrated circuit memory includes a memory cell having a ferroelectric capacitor, one electrode of which is connected to a bit line through a transistor, and the other electrode of which is connected to a plate line. The bit line is also connected to system ground through a precharge transistor. In a read cycle, the precharge transistor remains on after the word line goes high connecting the capacitor to the bit line. At least a portion of the linear displacement current that flows to the bit line is drained off to ground via the precharge transistor, thereby increasing the switching voltage across the ferroelectric capacitor. The precharge transistor is turned off before or during the switching of the ferroelectric capacitor. The signal applied to the gate of the precharge transistor is boosted above the supply voltage of the memory to shorten the cycle time.

Ferroelectric memory with increased switching voltage

A liquid precursor containing a metal is applied to a first electrode, dried in air at a first temperature of 160.degree. C. and then a second temperature of 260.degree. C., RTP baked at a temperature of 300.degree. C. in oxygen, RTP baked at a temperature of 650.degree. C. in nitrogen, and annealed at a temperature of 800.degree. C. in nitrogen to form a strontium bismuth tantalate layered superlattice material. A second electrode is deposited and then the device is patterned to form a capacitor, and a second anneal is performed at a temperature of 800.degree. C. in nitrogen. Alternatively, the second anneal may be performed in oxygen at a temperature of 600.degree. C. or less. In this manner, a high electronic quality thin film of a layered superlattice material is fabricated without a high-temperature oxygen anneal.

Process for fabricating layered superlattice materials and AB0.sub.3

A precursor liquid comprising several metal 2-ethylhexanoates, such as strontium, tantalum and bismuth 2-ethylhexanoates, in a solvent such as xylenes/methyl ethyl ketone and a small amount of hexamethyl-disilazane. The liquid is dried, baked, and annealed to form a thin film of a layered superlattice material, such as strontium bismuth tantalate, on the substrate.

Liquid source formation of thin films using hexamethyl-disilazane

A precursor liquid comprising several metal 2-ethylhexanoates, such as strontium, tantalum and bismuth 2-ethylhexanoates, in a xylenes/methyl ethyl ketone solvent is prepared, a substrate is placed within a vacuum deposition chamber, a small amount of hexamethyl-disilazane is added to the precursor liquid is misted, and the mist is flowed into the deposition chamber while maintaining the chamber at ambient temperature to deposit a layer of the precursor liquid on the substrate. The liquid is dried, baked, and annealed to form a thin film of a layered superlattice material, such as strontium bismuth tantalate, on the substrate. Then an integrated circuit is completed to include at least a portion of the layered superlattice material film in a component of the integrated circuit.

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Colorado Springs, CO, United States of America

Gary F Derbenwick