Tandem Computers Incorporated

Gary F Campbell

Robert W Horst

David J Garcia

William P Bunton

William J Watson

David P Sonnier

William Edward Baker

Richard W Cutts, Jr

Geoffrey I Iswandhi

Daniel L Fowler

Frank A Williams

Paul N Hintikka

Murali Basavaiah

John Michael Brown

John D Coddington

John C Krause

William F Bruckert

Douglas E Jewett

Susan S Meredith

Steven C Meyers

Stephen G Low

Srinivasa D Murthy

Patricia L Whiteside

Linda Ellen Zalzala

Randall G Banton

James Stevens Klecka

Curtis Willard Jones, Jr

Joseph D Kinkade

Barry Lee Drexler

Harry Frank Elrod

A multiprocessor system includes a number of central processing unit (CPUs) and at least one input/output (I/O) device interconnected by routing apparatus for communicating packetized messages therebetween. The messages contain address information identifying the source and destination of the message, and may also contain requests to write to, or read from, storage of a CPU. Protection against errant reads or writes is provided by an access validation method that utilizes access validation information contained in plural entries maintained by each CPU. Each entry provides validation by identifying what elements of the system has read and/or write wccss to the memory of that CPU, without which memory access is denied.

Storage access validation to data messages using partial storage address

A multiprocessor system is configured so that each of the central processing units (CPUs) of the system have accessed at least portions of the memory of each other CPU. Interprocessor messaging is conducted by a CPU writing to, or reading from, the memory of another CPU of the system.

Interprocessor messaging system

A multiprocessor system includes a number of sub-processor systems, each substantially identically constructed, and each comprising a central processing unit (CPU), and at least one I/O device, interconnected by routing apparatus that also interconnects the sub-processor systems. A CPU of any one of the sub-processor systems may communicate, through the routing elements, with any I/O device of the system, or with any CPU of the system. The CPUs are structured to operate in one of two modes: a simplex mode in which the two CPUs operate independently of each other, and a duplex mode in which the CPUs operate in lock-step synchronism to execute each instruction of identical instruction streams at substantially the same time. Communications between I/O devices and CPUs is by packetized messages. Interrupts from I/O devices are communicated from the I/O devices to the CPUs (or from one CPU to another CPU) as message packets. CPUs and I/O devices may write to, or read from, memory of a CPU of the system. Memory protection is provided by an access validation method maintained by each CPU in which CPUs and/or I/O devices are provided with a validation to read/write memory of that CPU, without which memory access is denied.

Fail-fast, fail-functional, fault-tolerant multiprocessor system

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Palo Alto, CA, United States of America

Gary F Campbell