Triquint Semiconductor Corporation

Triquint, Inc.

Gary D McCormack

William H Davenport

Stewart S Taylor

George S LaRue

Patrick J Hamilton

An integrating phase detector includes a phase comparator and an integrating load impedance. The phase comparator is a voltage-input, current-output logic gate such as a OR/NOR gate, or a XOR/XNOR gate having first and second inputs for comparing the phase of first and second input signals. The current output of the logic gate provides an output current pulse proportional to the phase difference between the first and second input signals. The integrating load such as a passive resistor-capacitor network is coupled to the current output of the phase detector for directly integrating the current pulse and providing a DC voltage proportional to the phase difference between the first and second input signals. The minimum pulse width of the output current pulse is substantially limited only by the fT of the devices used in the logic gate. The improved bandwidth of the phase detector also increases the linear operating range by increasing the range of phase in which the output current pulse is proportional to the input phase difference.

Integrating phase detector

An apparatus and method for improving the bit error rate of multiplexed signals in a multiplexer system includes independently controlling two types of timing errors. The first type of timing error is related to the timing of transitions between alternating portions of the multiplexed output signal. The second type of timing error is related to the amplitude of the crossing points of the multiplexed signal portions. Varying the duty cycle of the clock signal to the multiplexer controls the transition between the alternating portions of the multiplexed output signal, and adding a voltage offset between single-ended components of the multiplexed output signal controls the amplitude of the crossing points between the one/zero and zero/one transitions of the multiplexed outut signal. The two types of timing errors are controlled with two separate control voltage ports that are independently and continuously variable in order to achieve the optimum bit error rate.

High performance multiplexer for improving bit error rate

A differential amplifier includes a pair of input transistors for directing portions of a load current from a current source through a pair of load transistors in response to a differential input signal. A common mode output voltage of the differential amplifier is detected and applied to control terminals of a pair of feedback transistors. The feedback transistors couple the load transistors to a reference voltage and act therewith to provide control currents through the load transistors concurrent with the load currents. The control currents provide feedback that maintains the common mode output voltage at a constant threshold level.

Differential amplifier with common-mode bias feedback

An integrated logic circuit comprises a direct coupled FET logic input stage and a super buffer logic output stage. The input stage comprises a depletion-mode FET having its drain connected to a first reference potential level and having its gate and source connected together, and a first enhancement mode FET structure having its drain connected to the source of the depletion-mode FET, its source connected to a second, lower reference potential level and having at least one gate connected to receive an input logical signal. The super buffer logic output stage comprises a second enhancement mode FET structure that is essentially identical to the first enhancement mode FET structure, the source of the second enhancement mode FET structure being connected to the second reference potential level and the gate of the second enhancement mode FET structure being connected to the gate of the first enhancement mode FET structure. The output stage also comprises a controllable current source connected between the source of the depletion-mode FET and the drain of the second enhancement mode FET structure, for providing drain current to the second enhancement mode FET structure when the potential of the drain of the first enhancement mode FET structure exceeds a predetermined level, and depriving the second enhancement mode FET structure of drain current when the drain of the first enhancement mode FET structure is below the predetermined potential level.

Growing community of inventors

Aloha, OR, United States of America

Gary D McCormack