International Rectifier Corporation

Applied Micro Circuits Corporation

Chil Semiconductor Corporation

Gary D Martin

Robert T Carroll

Venkat Sreenivas

Praveen Jain

James Noon

William Anker

Anthony B Candage

Narendra K Bansal

According to example configurations as described herein, a power supply system includes a unique circuit including an analog summer circuit, an analog-to-digital converter, and a digital controller. An output voltage feedback control loop of the power supply system feeds back the output voltage to the analog summer circuit. The analog summer circuit generates an analog error voltage signal based on: i) the output voltage received from the output voltage feedback loop, ii) an analog reference voltage signal, and iii) an analog reference voltage adjustment signal. The analog reference voltage adjustment signal varies depending on a magnitude of current provided by the output voltage to the dynamic load. Accordingly, the analog summer circuit can be configured to support adaptive voltage positioning. The analog-to-digital converter converts the analog error voltage signal into a digital error voltage signal. A controller generates output voltage control signal(s) based on the digital error voltage signal.

Hybrid analog/digital power supply circuit including analog summer circuit to produce an error voltage

According to one configuration, a controller repeatedly loads a time delay circuit with a predetermined (count) value. The predetermined count value specifies an approximate time delay between activating and/or deactivating high side switch circuitry of one or more phases in the power supply. Based on passing of time as indicated by the time delay circuit, the controller generates control signals to control high side switch circuitry (of a same or different phase) in the power supply. The high side switch circuitry in one or more phases can be successively activated or spaced in time by an approximate amount of time as specified by the predetermined (count) value.

Control signal generation and power supply circuitry

A power supply system includes multiple power converter phases. A controller (e.g., a processor device) monitors energy delivery for each of multiple power converter phases that supply energy to a load. The controller analyzes the energy delivery associated with each of the multiple power converter phases to identify an imbalance of energy delivered by the multiple power converter phases to the load. Based on the analyzing and detection of an imbalance condition, the controller modifies a future order of activating the multiple power converter phases for powering the load. Accordingly, a single phase of a multiphase switching power converter may be prevented from becoming overloaded while delivering energy to power the load.

Modification of activation order in a multi-phase power delivery system

According to one configuration, a multi-phase power supply adjusts a number of active phases based at least in part on a peak current supplied to a dynamic load. For example, a controller associated with the multi-phase power supply can monitor or receive a value indicative of a peak magnitude of current delivered by the multi-phase power supply to a dynamic load. The controller initiates comparison of the value to threshold information. Based at least in part on the comparison, the controller adjusts how many phases of the multi-phase power supply are activated to deliver the current delivered to the dynamic load. Thus, one embodiment herein is directed to controlling a multi-phase power supply based at least in part on a measured parameter such as peak current magnitude.

Power supply circuit and multi-phase control based on peak and average current

In an example configuration, a power supply manager receives an output current value representing an amount of output current supplied by one or more power converter phases to a load. The power supply manager also receives a duty cycle value representing a duty cycle for controlling operation of the at least one power converter phase. The power supply manager produces an estimate of input current supplied to the power supply circuit based at least in part on multiplying the output current value by the duty cycle value. Contrary to conventional methods such as physically measuring an input current using complex measuring circuitry, embodiments herein include utilizing parameter information such as output current information and duty cycle information to deduce an amount of input current.

Power supply circuitry, collection and reporting of power supply parameter information

Modification of switch activation order in a power supply

A power supply system delivers current to a load at a corresponding load voltage. The power supply system includes multiple power converter phases. Each power conversion phase comprises a phase switch and a phase inductor. In one embodiment, activation of a corresponding phase switch (e.g., a field effect transistor such as a MOSFET) electrically couples a voltage input (e.g., Vin) to an inductor electrically coupled to deliver current to a load. A controller (e.g., a processor device) associated with the power supply system is configured to monitor the load and/or a change in the current delivered to the load. Based on the monitoring, the controller modifies a relative timing of an initiation and duration of on-times of the phase switches in order to alter a rate-of-change of the current delivered by the power supply system.

Power supply and controller circuits

A power supply system includes multiple power converter phases. A controller (e.g., a processor device, ASIC) monitors an output voltage generated by a combination of multiple power converter phases that supply power to a load. Based on the monitoring, the controller determines: i) a magnitude of an error signal representing a relative difference between the output voltage and a predetermined setpoint value, and ii) a rate-of-change associated with the output voltage. The controller compares the rate-of-change to threshold criteria. In response to detecting that the rate-of-change associated with the output voltage exceeds a threshold value, the controller adjusts a time of turning on of a phase switch (e.g., a power switch configured to convey an input voltage to an inductor that in turn delivers energy to the load) in one or more of the multiple power converter phases depending on the magnitude of the error signal.

An architecture for a high bandwidth digital cross-connect switching system that is internally non-blocking, has a simpler layout, and employs a reduced number of logic gates. The high bandwidth digital cross-connect switching architecture comprises a Time Division Multiplexing (TDM) cross-connect including M space/time switches. Each space/time switch includes an input bus, an output bus, N&#xd7;W Flip-Flops (FFs) for storing input data, W N-by-N switches for sorting the data according to predetermined cross-connection requirements, and N&#xd7;W FFs for storing output data, in which 'N' corresponds to the number of input ports and the number of output ports in the N-by-N switch, and 'W' corresponds to the width of each data word. Each N-by-N switch includes N&#xd7;W N-to-1 selectors, and the M space/time switches include N&#xd7;W M-to-1 selectors, thereby allowing an effective N&#xd7;M-to-1 selection to be performed on the data words.

Pipeline architecture for the design of a single-stage cross-connect system

A SONET multiplexed system architecture that permits greater levels of integration. The architecture includes a time slot interchanger for routing information from at least one SONET input signal path associated with a respective first time slot to at least one SONET output signal path associated with a respective second time slot. Each input signal path includes a pointer interpreter, and each output signal path includes a FIFO buffer serially coupled to a pointer generator. The architecture further includes a synchronization buffer in each input signal path for transferring the input signal to the clock rate of the time slot interchanger. The architecture permits greater levels of integration when the time slot interchanger has more inputs than outputs, and/or the time slot interchanger provides the output signal to a pointer processor to transfer the output signal to the clock rate of the output signal path.

Time slot interchanging of time slots from multiple SONET signals without first passing the signals through pointer processors to synchronize them to a common clock

An encryption system has been provided to self-synchronously scramble communications where the receiver must recover the clock information from the data stream, such as the SONET format. To prevent jamming during initialization, or during times when no data is being transferred, flags and overhead data are scrambled, along with the payload. Timing controls to the scrambler permit this scrambler to be selectively engagable, so that the selective overhead scrambling becomes a second layer of scrambling. A method of self-synchronously scrambling the overhead in NRZ formatted communications is also provided.

Self-synchronous data scrambler

A SONET multiplexed communications system that facilitates the sharing of processing resources while reducing overall system complexity. The SONET multiplexed communications system includes a single multi-output pointer generator clocked by a system clock and a plurality of clock domain transfer circuits having respective FIFO buffers for transferring SONET signals from the system clock domain to respective outgoing line clock domains. The multi-output pointer generator and the clock domain transfer circuits compensate for timing differences between the system clock and the respective outgoing line clocks by either skipping or overwriting FIFO buffer address locations corresponding to TOH byte positions in outgoing SONET frames. The TOH bytes corresponding to the skipped or overwritten TOH byte positions are subsequently re-generated by respective TOH insertion circuits before the outgoing SONET frames are passed through outgoing SONET lines.

Growing community of inventors

Boxford, MA, United States of America

Gary D Martin