3com Corporation

Gary D Lorenz

Charles R Weaver

Brian J Myrick

Brian Ramelson

Frank A Itkowsky

Cary B Robins

Bruce W Thompson

Charles Lee

Andreas Bovopoulos

Peter Driscoll

A switching architecture for very high data rates which is placed between a port connecting to a fiber optic gigabit ethernet link and a two Gbit/sec backplane of a concentrator. A port connects to the link for both receiving and transmitting data packets from and to the link. A first FTE receives a data packet from the port, and analyzes the data packet to determine if the data packet should be forwarded to the backplane of the concentrator. If the data packet is to be forwarded, the first FTE sends the data packet to a backplane connection for connecting to the backplane of the network concentrator. A second FTE is connected to the backplane connection. The second FTE receives a data packet from the backplane connection, and analyzes the data packet in a manner similar to the first FTE to determine if a packet should be forwarded to the port. The process of the second FTE with regard to the data packets is substantially similar to the process of the first FTE, except that it is determined whether or not the data packets from the backplane should be forwarded to the port. This switch architecture therefore uses separate transmit and receive channels with independent forwarding tables. The first and second FTE's can be substantially identical, and are preferably switch engine ASIC's (Application Specific Integrated Circuit) designed for a lower data rate.

High speed switch architecture using separate transmit and receive channels with independent forwarding tables

A self-starting brushless electric motor having: a first motor part (stator) (11) with poles (15S, 16A) arranged in a first pole row, said poles comprising for each winding phase a pole group (13) including a pole pair consisting of a reluctance pole (15S) and a permanent-magnet pole (16A), only one such pole group being provided for each winding phase; a second motor part (rotor) (12) movable with respect to the first motor part (11) and provided with reluctance poles (18A) arranged in a second row of poles opposite to the first row of poles; and a magnetizing winding (17) on the first motor part (11). At least one of the pole rows exhibits a magnetic asymmetry providing a preferential relative direction of movement of the motor parts (11, 12) upon energization of the winding. The poles (15S, 16A) of the pole pair of the first pole row are spaced-apart such that whenever a pole of the pair is magnetically aligned with a pole (18A) of the second pole row, the other pole of the pair is magnetically misaligned with the next adjacent pole of the second pole row. A ferromagnetic auxiliary pole means (20) is provided on the first motor part (11) and positioned such that whenever the permanent-magnet pole (16A) of said pair is magnetically aligned with a pole (18A) of the second pole row, the auxiliary pole means (20) confronts at least one of the other poles of the second pole row across an air gap (19) which separates the pole rows.

Method and device for generating a frame check sequence

A plural interface LAN switch arbitration method dividing access to a packet memory into a plurality of sequential cycles. A refresher is provided for refreshing the packet memory and the refresher issues a refresher request when the refresher needs to access the packet memory. A first and second interface are provided for transferring data between the packet memory and the respective first and second LAN's. The first and second interface issue a respective first and second interface request when the respective interface needs to access the packet memory. A processor is provided for updating the packet memory and issues a processor request when the processor needs to access the packet memory. The arbitration provides the refresher with an immediately next cycle of the memory when the refresher request is present. The arbitration method also provides the processor with an immediately next cycle of the packet memory when the processor request is present and the refresher has a present cycle which guarantees the processor periodic access to the memory.

LAN switch interface for providing arbitration between different

A VLAN memory access system to provide VLAN address table look-ups with the ability to simultaneously do processor read cycles or processor write cycles to the same memory structure with anatomical accesses. The system encompasses the interaction between a memory look-up table that stores the slot allowed transition bit mask for a multi-slot hub based VLAN switch, a switch processor interface that is used to upgrade the memory access table by writing entries into the table or reading the table to verify its contents, and a look-up processor that uses the VLAN table to make forwarding decisions on the destination of a packet based on the value read from the VLAN memory look-up table. The VLAN table accesses must be arbitrated between the look-up processor, which has the highest priority, and read or write accesses from the switch processor. The look-up processor takes the VLAN ID field of a packet and uses this as the address of the slot allowed transmit bit mask to be applied to the destination slot bit mask. This logical AND function is used to determine the final bit mask of slots that will receive this packet.

Virtual local area network memory access system

A computer network system containing a concentrator with a backplane that has a plurality of lines. The backplane contains data lines and control lines for managing and organizing the transfer of data between modules in the concentrator. The system contains intelligent devices that allow the selection of transmitting modules to occur at the same time as actual data transfer is going on between other modules. This is preferably done in a round robin arbitration process where, while data is being transferred by a first module, a bus arbitration device is placing addresses of modules which sequentially follow the transmitting module onto the control lines. Modules will see their address on the control lines, and if they have a packet to transmit, they then reserve the right to transmit after the presently transmitting module is finished. In this way the selection of the next module to transmit is performed in parallel, and does not slow down, the transfer of data between modules. The control lines are also able to indicate when a receiving module has been unable to copy a packet. The transmitting module can then resend the packet for either a maximum number of retries, or until the receiving module is able to copy the packet.

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Acton, MA, United States of America

Gary D Lorenz