Sperry Corporation

Gary D Burns

Scott D Schaber

James H Scheuneman

Donald W Mackenthun

Within a High Performance Storage Unit (HPSU) digital memory resource, plural ones (up to 4) of a multiplicity (nominally 8) of independently operative storage memory banks, each consisting of four storage modules, are each simultaneously communicating voluminous read data (nominally 144 data bits plus 16 parity bits) read from each to a respective one of plural (nominally 4) output ports of the memory resource, said communicating being upon and via a selected one of a like plural number (4) of wired-OR communication buses. Priority control does assure that all (up to 4 such) of the (8) storage memory banks simultaneously reading data are (1) each doing so responsively to a request arising upon a different one of (4) memory resource input ports, and are (2) each controlled to selectively emplace the data read upon one only of a multiple number (4) of output ports of the (8) storage memory banks, and the (4) storage modules within each of the (8) storage memory banks--respective ones of each of the (4) storage memory bank ports connecting to a respective one of the four (4) wired-OR communication buses.

Multiple output port memory storage module

An improved dynamic memory system including through-checking and error detection of the refresh counter is described. A refresh counter that provides parity of the refresh count for through-checking, of refresh addresses is shown. Error detecting circuitry is utilized in conjunction with the refresh counter and the parity generating circuitry to detect errors in functionality of the refresh counter. The refresh counter is a Gray code counter constructed of a double rank of latches operable with code generating logic circuits for determining the sequence of generation of Gray code groupings.

Gray code counter with error detector in a memory system

An improved error indicating system utilizing adder circuits for use with an error correction code system capable of detecting and indicating multiple bit errors and detecting and correcting single bit errors is described. The system utilizes an encoding system for generating a plurality of check bits, each check bit associated with a predetermined bit grouping of data bits within a data word. When a data word is accessed, read check bits are reconstituted from the read data and are compared to the check bits originally encoded. Syndrome bits are generated from the originally encoded check bits and the reconstituted read check bits, the syndrome bits thus generated, serving to identify whether the data word accessed contains no errors, a single bit error, or a multiple bit error. Decoder circuitry for decoding the syndrome bits and effecting the control signals for controlling the correction of single bit errors is described. The syndrome bits are applied to the adder circuits in predetermined groupings, and the carry signals from each of the adder circuits are applied to circuitry for detecting the occurrence of multiple bit errors. Selected ones of the decoded syndrome bits are utilized to determine the occurrence of single bit errors.

Growing community of inventors

Cottage Grove, MN, United States of America

Gary D Burns