Lsi Logic Corporation

Qualcomm Incorporated

Advanced Micro Devices Corporation

Lsi Corporation

Gary Chang

Ho-Ming Leung

Richard Dominic Wietfeldt

Lalan Jee Mishra

Mohit Kishore Prasad

Amit Gil

Helena Deirdre O'Shea

Chiu-Tsun Chu

Fan Zhang

Wern-Yan Koe

Moon S Kok

May-Lin Lee

Vinay Jain

Jiunn-Yau Liou

Omer F Orberk

Hong-men Su

Systems, methods, and apparatus are described that provide for communicating coexistence messages over a multi-drop serial bus. A data communication method includes configuring a common memory map at each of a plurality of devices coupled to a serial bus, receiving at a first device coupled to the serial bus, first coexistence information directed to a second device coupled to the serial bus, generating at the first device, a coexistence message that includes the first coexistence information, and transmitting the coexistence message to the second device over the serial bus. The first coexistence information in the coexistence message may be addressed to a location in the common memory map calculated based on a destination address associated with the first coexistence information and a unique identifier of the first device.

Function-specific communication on a multi-drop bus for coexistence management

In a device comprising a serial bus and a plurality of devices, register/address mappings and/or unique group identifiers are used to convey additional information in messages/datagrams over the serial bus without explicitly sending such information in the message/datagram. Such register/address mappings may be done beforehand, and in conjunction with group-specific identifiers, may reduce transmission latency by keeping the size of the messages/datagrams small. Since all devices on the serial bus have prior knowledge of such register/address mappings and/or group-specific identifiers, recipient devices are able to infer information from the group-specific identifiers and/or register/address sent in each message/datagram that is not explicitly sent within such message/datagram.

Efficient technique for communicating between devices over a multi-drop bus

An apparatus comprising a buffer circuit, a rotation circuit and a memory. The buffer may be configured to store original image data in one or more sub-matrices. The rotation circuit may be configured to (i) produce rotated data and (ii) store the rotated data in a transposed matrix. The memory may be configured to position the rotated data in the transposed matrix. The transposed matrix comprises final image data rotated by a predetermined angle from the original image data.

Efficient and high speed 2D data transpose engine for SOC application

One aspect of the present invention concerns a method for controlling the frequency of oscillation of a local clock signal comprising the steps of (A) generating the clock signal in response to a first control signal, (B) generating the first control signal in response to one of a plurality of adjustment signals selected in response to a second control signal and (C) generating the second control signal in response to a comparison between a local timestamp and an external timestamp.

Integrated circuit with on-chip clock frequency matching to upstream head end equipment

An apparatus comprising (i) a first circuit configured to generate one or more node signals at one or more internal nodes and (ii) a second circuit configured to present one or more of the node signals and a trigger signal in response to one or more control signals.

Built-in debug feature for complex VLSI chip

An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to transfer data between a plurality of first ports and a second port via a single port memory in response to one or more control signals. The second circuit may be configured to generate the one or more control signals, wherein the memory is time shared among the second port and the plurality of first ports.

Time sharing a single port memory among a plurality of ports

The circuit provides one or several banks of capacitors, the capacitors in each bank being identical in size. A single fuse for each bank of capacitors controls the connection of the capacitors to a pulse-width-determining node on each of the ATD (address-transition-detect) pulse generators of the SRAM device. Depending on the position of the fuse in the circuit, the blowing of a single fuse can either add to the capacitance at the ATD nodes or substract from it. Thus the pulse-width of all ATD pulse generators can be adjusted shorter or longer simultaneously by blowing a single fuse only.

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San Jose, CA, United States of America

Gary Chang